VSC7212 Datasheet, PDF (23/34 Pages) Vitesse Semiconductor Corporation – Gigabit Interconnect Chip

VIITTEESSSSEE
SEEMMIICCOONNDDUUCCTTOORRCCOORPROPROARTAIOTNION
Preliminary Data Sheet
VSC7212
Gigabit Interconnect Chip
Figure 19: RCLK and RCLKN Timing Waveforms with DUAL = 1
RCLK
T₄
T₃
RCLKN
Table 14: General Receive AC Characteristics
Parameters
T₃
DT₃
T₄
DT₄
T_R, T_F
R_LAT
T_LOCK(1)
T_JTD
D_JTD
Description
Delay between rising edge of
RCLK to rising edge of
RCLKN
RCLK to RCLKN skew
Delay=
----1---0----
f_baud
±
∆T₃
Period of RCLK and
RCLKN
Deviation of
RCLK/RCLKN period from
REFCLK period
T_RCLK= T_REFCLK ± ∆T₄
Output rise and fall time
Latency from RX0 to
REFCLK or RCLK
Data acquisition lock time
Receive data Total
Jitter Tolerance (p-p)
Receive data Deterministic
Jitter Tolerance (p-p)
Min.
10 x T_RX
-500
-500
0.49 x
T_REFCLK
-1.0
—
70.5bc-1.6ns
48.5bc-1.6ns
—
—
—
Max.
10 x T_RX
+500
500
0.51 x
T_REFCLK
1.0
2.4
81.5bc+4.1ns
102.5bc+4.1ns
2500
600
370
Units
ps
ps
ps
%
ns
bc+ns
bc
ps
ps
Conditions
T_RX is the bit period of the
incoming data on Rx.
Deviation of RCLK rising
edge to RCLKN rising edge.
Nominal delay is 10-bit
times.
Whether or not locked to
serial data, independent of
DUAL input.
Whether or not locked to
serial data, independent of
DUAL input.
Between V_IL(MAX) and
V_IH(MIN) into 10pF load
ENDEC=1, recenter only
ENDEC=X, recenter + drift
8B/10B IDLE pattern,
Tested on a sample basis.
IEEE 802.3z Clause 38.68,
tested on a sample basis.
IEEE 802.3z Clause 38.69,
tested on a sample basis.
NOTE: (1) The probability of correct data acquisition and recovery is 95% per FC-PH 4.3 Section 5.3.
G52268-0, Rev 3.3
04/10/01
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