TA1317AFG Datasheet, PDF (52/58 Pages) Toshiba Semiconductor – Deflection Processor IC for TV

Note
No.
Parameter
42 Analog blanking phase
TA1317AFG
SW6
ON
SW7
A
SW8
OFF
Test Condition
SW Mode
SW10 SW13 SW14 SW21 SW30
Test Method
(unless otherwise specified, V_CC = 9 V, Ta = 25 ± 3°C, data = preset values)
OFF B
ON
A
A (1) Input vertical trigger pulse to pin V_IN.
Pulse level (VT) = 3.0 V, 60Hz
(2) Set VD (sub-address: 00) to DC-Coupling mode (data: 80).
(3) Set V INTEGRAL CORRECTION (sub-address: 08) to center (data: 8F).
(4) Set V S CORRECTION (sub-address: 09) to center (data: A0).
(5) AS shown in the figure below, measure analog blanking phase in relation to pin 26
(V_IN) under the following conditions.
(6) Set ANALOG V-BLK STOP PHASE (sub-address: 03) to minimum (data: 00) and
measure blanking phase BLHL.
(7) Set ANALOG V-BLK STOP PHASE (sub-address: 03) to center (data: 80) and
measure blanking phase BLHM.
(8) Set ANALOG V-BLK STOP PHASE (sub-address: 03) to maximum (data: F8) and
measure blanking phase BLHH.
(9) Set ANALOG V-BLK START PHASE (sub-address: 04) to minimum (data: 00) and
measure blanking phase BLLL.
(10) Set ANALOG V-BLK START PHASE (sub-address: 04) to center (data: 80) and
measure blanking phase BLLM.
(11) Set ANALOG V-BLK START PHASE (sub-address: 04) to maximum (data: F8) and
measure blanking phase BLLH.
Vertical trigger pulse
Pin 24 (BLK OUT)
BLLL BLHL
BLLM BLHM
BLLH BLHH
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2005-08-18