TA1317AFG Datasheet, PDF (12/58 Pages) Toshiba Semiconductor – Deflection Processor IC for TV

Register Name/Number of Bits
V CENTERING/7
Function Explanation
Where VD = 0, DC level of V-DRIVE is adjusted. Where VD =
1, DAC output level of pin 2 is set.
0000000: min
1000000: center
1111111: max
Output Change
Pin 7(VD = 0)
V-DF PHASE/4
Adjusts the phase of the vertical dynamic focus output.
0000: min
1000: center
1111: max
V-DF AMPLITUDE/4
H-DF PHASE/4
Adjusts the amplitude of the vertical dynamic focus output.
0000: min
1000: center
1111: max
Adjusts the phase of the horizontal dynamic focus output.
0000: min
1000: center
1111: max
Pin 22
Pin 22
Pin 20
Picture Change
TA1317AFG
Preset
Solid line
Dashed line
VD = 0
min
(0000000)
center
⎯
(1000)
center
⎯
(1000)
center
⎯
(1000)
12
2005-08-18