TA1317AFG Datasheet, PDF (48/58 Pages) Toshiba Semiconductor – Deflection Processor IC for TV

TA1317AFG
Note
No.
32
Parameter
Vertical DF phase adjustment
(V DF phase)
SW6
OFF
SW7
B
SW8
ON
Test Condition
SW Mode
SW10 SW13 SW14 SW21 SW30
Test Method
(unless otherwise specified, V_CC = 9 V, Ta = 25 ± 3°C, data = preset values)
OFF B
ON
A
A (1) Input vertical trigger pulse to pin V_IN.
Pulse level (VT) = 3.0 V
(2) Set V-DF PHASE (sub-address: 06) to minimum (data: 08) and measure pin 22
(V-DF OUT) phase T_VD (08).
(3) Set V-DF PHASE (sub-address: 06) to maximum (data: F8) and measure pin 22
(V-DF OUT) phase T_VD (F8).
(4) Calculate change amount T_VD using the following formula.
33 LVP detection voltage
OFF
B
ON OFF B
34 Vertical guard detection
voltage
OFF C
ON OFF B
35 Vertical guard detection
output current
(BLK-OUT output current)
OFF C
ON OFF B
36 Vertical centering DAC output OFF
B
voltage 1 (V centering)
ON OFF B
37 Vertical centering DAC output OFF
A
OFF OFF
B
voltage 2 (V shift)
ON
B
ON
A
ON
A
ON
A
ON
A
T_VD = T_VD (08) + T_VD (F8)
A (1) Connect external supply voltage V₈ to TP21 (LVP).
(2) Decrease external supply voltage V₈ from 9 V. When D5 data in Read mode
changes from 0 to 1, measure TP21 voltage V_LVP.
A (1) Connect external supply voltage V₇ to TP7 (V NF).
(2) Switch to VD (sub-address: 00) to AC-Coupling mode (data: 81).
(3) Increase external supply voltage V₇ from 5.5 V. When D3 data in Read mode
changes from 0 to 1, measure TP7 voltage V_VGH.
(4) Decrease external supply voltage V₇ from 5.5 V. When D3 data in Read mode
changes from 0 to 1, measure TP7 voltage V_VGL.
A (1) Connect external supply voltage V₇ = 8 V to TP7 (V NF).
(2) Measure pin 24 (BLK OUT) voltage V₂₄ and calculate output current (I₂₄) using the
following formula.
V₂₄
I₂₄ =
10 kΩ
A (1) Set VD (sub-address: 00) to AC-Coupling mode (data: 81).
(2) Set V CENTERING (sub-address: 05) to minimum (data: 00) and measure pin 2
(CENTER DAC) voltage V_CA (00).
(3) Set V CENTERING (sub-address: 05) to maximum (data: FE) and measure pin 2
(CENTER DAC) voltage V_CA (FE).
A (1) Set VD (sub-address: 00) to DC-Coupling mode (data: 80).
(2) Set V SHIFT (sub-address: 01) to minimum (data: 80) and measure pin 2 (CENTER
DAC) voltage V_CD (80).
(3) Set V SHIFT (sub-address: 01) to maximum (data: 83) and measure pin 2
(CENTER DAC) voltage V_CD (83).
48
2005-08-18