TA1317AFG Datasheet, PDF (18/58 Pages) Toshiba Semiconductor – Deflection Processor IC for TV

Data Transmit Format 1
TA1317AFG
S Slave address
7 bit
MSB
S: Start condition
0A
Sub address
8 bit
MSB
A: Acknowledge
A Transmit data
9 bit
MSB
AP
P: Stop condition
Data Transmit Format 2
S Slave address 0 A Sub address A Transmit data A ･･････
･･････ Sub address A Transmit data n A P
Data Receive Format
S Slave address
7 bit
MSB
1A
Receive data
8 bit
MSB
ΑP
At the moment of the first acknowledge, the master transmitter becomes a receiver and the slave receiver becomes
a transmitter.
The Stop condition is generated by the master.
Optional Data Transmit Format: Automatic Increment Mode
S Slave address
7 bit
MSB
0A1
Sub address
7 bit
MSB
A Transmit data 1
8 bit
MSB
････ Transmit data 2
8 bit
MSB
AP
In this transmission method, sub-addresses are incremented automatically and data is set from the specified
sub-address.
I²C BUS Conditions
Characteristics
Low level input voltage
High level input voltage
Low level output voltage at 3 mA sink current
Input current each I/O pin with an input voltage
between 0.1 VDD and 0.9 VDD
Capacitance for each I/O pin
SCL clock frequency
Hold time START condition
Low period of SCL clock
High period of SCL clock
Set-up time for a repeated START condition
Data hold time
Data set-up time
Set-up time for STOP condition
Bus free time between a STOP and START condition
Symbol
V_IL
V_IH
V_OL1
I_i
C_i
f_SCL
t_HD;STA
t_LOW
t_HIGH
t_SU;STA
t_HD;DAT
t_SU;DAT
t_SU;STO
t_BUF
18
Min Typ. Max Unit
0
⎯
1.5
V
2.7
⎯
Vcc
V
0
⎯
0.4
V
−10 ⎯
10
µA
⎯
⎯
10
pF
0
⎯ 100 kHz
4.0
⎯
⎯
µs
4.7
⎯
⎯
µs
4.0
⎯
⎯
µs
4.7
⎯
⎯
µs
100 ⎯
⎯
ns
250 ⎯
⎯
ns
4.0
⎯
⎯
µs
4.7
⎯
⎯
µs
2005-08-18