TA1318N Datasheet, PDF (33/41 Pages) Toshiba Semiconductor – TOSHIBA Bipolar Linear Integrated Circuit Silicon Monolithic

Note
Item
VA01
VD1 input threshold voltage
VD2 input threshold voltage
VD3 input threshold voltage
(SW block)
VA02 VD3 input threshold voltage
(synchronization block)
TA1318N
SW Mode
S06 S18 S19 S21
Test Conditions and Measuring Method (V_CC = 9 V, Ta = 25 ± 3 C, unless otherwise specified)
c
b

 (1) Set sub-address (00) 80.
(2) Input Signal a (vertical 60 Hz) to pin 4 (VD1-IN).
(3) Set sub-address (02) 00.
(4) Increasing the voltage of Signal a from 0 V. measure the voltage of Signal b V_thVD1 when VD1-OUT lock.
(5) Measure V_thVD2 and V_thVD3 against pin 2 and pin 10 as wall.
Signal a
16.67 ms
0.12 ms
V_thVD1
c
b

 (1) Set sub-address (00) 70.
(2) Input Signal b (vertical 60 Hz) to pin 10 (VD3-IN).
(3) Set sub-address (02) 03.
(4) Increasing the voltage of Signal b from 0 V, measure the voltage of Signal a V_thVD3 when VD1-OUT lock.
Signal a
16.67 ms
0.12 ms
33
2003-02-19