TA1318N Datasheet, PDF (2/41 Pages) Toshiba Semiconductor – TOSHIBA Bipolar Linear Integrated Circuit Silicon Monolithic

Block Diagram
DAC3
24
DAC3
SW
VD2-OUT
23
VD1-OUT
22
SYNC1-IN
21
INV
INV
SYNC
SW
SW
SEPA
TEST DAC3 _DV2-OUT
SW
DV1-OUT
SW
DAC1
20
DAC1
SW
SYNC2-IN Address SW
19
18
SYNC
SEPA
DAC1
SCL
SDA
17
16
I²CBUS
Decoder
TA1318N
HD2-OUT Digital GND HD1-OUT
15
14
13
INV
INV
SW
SW
HD2-OUT
SW
HD1-OUT
SW
H/V-
FREQ
Counter
V-SYNC
V-FREQ
DET SW
H/C-
SYNK
DAC2
DAC2
SW
V-Input
SW
V
Integral
H-FREQ
DET SW
H-INPUT
SW
V C/D
V-FREQ
SW
Clamp
Pulse
HD
Polarity
H-AFC
HVCO
CP
SW
2 × f_H
H C/D
H-Ramp
H-FREQ
SW
1
2
3
4
5
6
7
8
9
10
11
12
HD2-IN
VD2-IN
HD1-IN
VD1-IN Analog GND AFC Filter
HVCO
V_CC
DAC2
VD3-IN
HD3-IN
CP-OUT
2
2003-02-19