TA1318N Datasheet, PDF (22/41 Pages) Toshiba Semiconductor – TOSHIBA Bipolar Linear Integrated Circuit Silicon Monolithic

Vertical Block
Characteristics
VD1 input threshold voltage
VD2 input threshold voltage
VD3 input threshold voltage
(SW block)
VD3 input threshold voltage
(synchronization block)
VD1 output voltage
VD2 output voltage
VD1 output voltage (polarity inverse)
VD2 output voltage (polarity inverse)
Vertical output pulse width
Symbol
V_thVD1
V_thVD2
V_thVD3
V_thVD3
V22TH0
V22TL0
V22TH1
V22TL1
V22TH2
V22TL2
V22TH3
V22TL3
V23TH0
V23TL0
V23TH1
V23TL1
V23TH2
V23TL2
V23TH3
V23TL3
V22IH0
V22IL0
V22IH1
V22IL1
V22IH2
V22IL2
V22IH3
V22IL3
V23IH0
V23IL0
V23IH1
V23IL1
V23IH2
V23IL2
V23IH3
V23IL3
VP_W0
VP_W1
VP_W2
VP_W3
Test
Circuit
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TA1318N
Test Condition
Min Typ. Max Unit
0.65 0.75 0.85
(Note VA01) 0.65 0.75 0.85 V_p-p
0.65 0.75 0.85
(Note VA02) 0.65 0.75 0.85 V_p-p
4.5
5.0
5.5

0.1
0.5
4.5
5.0
5.5

0.1
0.5

V
4.5
5.0
5.5

0.1
0.5
4.5
5.0
5.5

0.1
0.5
4.5
5.0
5.5

0.1
0.5
4.5
5.0
5.5

0.1
0.5

V
4.5
5.0
5.5

0.1
0.5
4.5
5.0
5.5

0.1
0.5
4.5
5.0
5.5

0.1
0.5
4.5
5.0
5.5

0.1
0.5

V
4.5
5.0
5.5

0.1
0.5
4.5
5.0
5.5

0.1
0.5
4.5
5.0
5.5

0.1
0.5
4.5
5.0
5.5

0.1
0.5

V
4.5
5.0
5.5

0.1
0.5
4.5
5.0
5.5

0.1
0.5
251 286 321
126 143 160
(Note VA03)
µs
117 133 150
88
100 112
22
2003-02-19