TA1318N Datasheet, PDF (14/41 Pages) Toshiba Semiconductor – TOSHIBA Bipolar Linear Integrated Circuit Silicon Monolithic

TA1318N
• HD1-INV (HD1 output polarity switch)
Switches HD1 output (pin 13) polarity. When set to 0, positive HD input is output as negative HD. When
set to 0, output from the sync circuit is output as negative HD.
*(0): Normal
(1): Inverse
• HD2-INV (HD2 output polarity switch)
Switches HD1 output (pin 15) polarity. When set to 0, positive HD input is output as negative HD. When
set to 0, output from the sync circuit is output as negative HD.
*(0): Normal
(1): Inverse
• V-FREQUENCY (Vertical frequency switch (pull-in range))
Sets vertical frequency pull-in range, VD-STOP, or free-running frequency.
Free-running frequency is controlled by H-FREQUENCY.
*(000)
(001)
(010)
(011)
(100)
(101)
(110)
(111)
Pull-in Range
48~1281 H
48~849 H
FREE-RUN
48~637 H
48~613 H
48~363 H
48~307 H
VP STOP
Format/H (V) Frequency
1125P/30 Hz (33.75 kHz)
750P/60 Hz (45 kHz)
Free-running frequency is controlled by H-FREQUENCY.
(00): 262 H (01): 525 H (10): 562 H (11): 750 H
1125I/60 Hz (33.75 kHz)
525P/60 Hz (31.5 kHz)
PAL/SECAM/50 Hz (15.625 kHz)
PAL/SECAM double scan/100 Hz (31.5 kHz)
NTSC/60 Hz (15.734 kHz)
NTSC double scan /120 Hz (31.5 kHz)
VD output is HIGH
• CLP PHS (Clamp pulse phase switch)
Switches clamp pulse phase.
If no signal input, 0.9 µs pulse is output from the H-C/D circuit.
*(0): 1 µs (3.4%) delay following HD stop phase, 0.8 µs (2.7%) pulse
(1): 0.5 µs (1.7%) delay following HD stop phase, 0.8 µs (2.7%) pulse
• FREQ DET SW (Horizontal/vertical frequency counter switch)
Switches input signal used for horizontal/vertical frequency counter. This switch is controlled
independently from INPUT SW. The detection result is output as read BUS data.
*(00): SYNC1 input (01): SYNC2 input (10)/(11): HD3/VD3 inputs
• INPUT SW (Input signal switch for synchronization)
Switches input signal used for synchronization.
*(00): SYNC1 input (01): SYNC2 input (10)/(11): HD3/VD3 inputs
• HD PHASE (HD phase adjustment)
Adjusts phase of HD output from the sync circuit. The phase of the adjustment center value is the same
as that of input H-SYNC or input HD. (Note) Synchronized VD width will change, when HD PHASE will
be changed.
(000000) : −5% (H periodically)
*(100000) : 0%
(111111) : 5%
• VD1-INV (VD1 output polarity switch)
Switches VD1 output (pin 22) polarity. When set to 0, negative VD input is output as negative VD. When
set to 0, output from the sync circuit is output as negative VD.
*(0): Normal
(1): Inverse
• VD2-INV (VD2 output polarity switch)
Switches VD2 output (pin 23) polarity. When set to 0, negative VD input is output as negative VD. When
set to 0, output from the sync circuit is output as negative VD.
*(0): Normal
(1): Inverse
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2003-02-19