TA1318N Datasheet, PDF (29/41 Pages) Toshiba Semiconductor – TOSHIBA Bipolar Linear Integrated Circuit Silicon Monolithic

Note
Item
HA08 Clamp pulse phase/width/level
TA1318N
SW Mode
S06 S18 S19 S21
Test Conditions and Measuring Method (V_CC = 9 V, Ta = 25 ± 3 C, unless otherwise specified)
c
b

 (1) Set sub-address (00) B0.
(2) Input Signal a (horizontal 33.75 kHz) to pin 11 (HD3-IN).
(3) Set sub-address (02) 02.
(4) Measure the clamp pulse phase (CP_S0), width (CP_W0), output level (CP_V0) of pin 12 (CLP-OUT) against
Signal a.
(5) Set sub-address (02) 12.
(6) Measure the clamp pulse phase (CP_S1), width (CP_W1), output level (CP_V1) of pin 12 (SCP-OUT) against
Signal a.
(7) Input no-signal to pin 11.
(8) Measure the clamp pulse phase (CP_S2), width (CP_W2), output level (CP_V2) of pin 12 (SCP-OUT) against pin
13 (HD-OUT).
Signal a
Pin 12 wave form
Pin 13 wave form
Pin 12 wave form
29.63 µs
2.35 µs
1.5 V
CP_S0ï½¥CP_S1
CP_V0ï½¥CP_V1
CP_W0ï½¥CP_W1
CP_S3
CP_V3
CP_W3
29
2003-02-19