TC94A04AFG Datasheet, PDF (29/42 Pages) Toshiba Semiconductor – 1 chip Audio Digital Processor

TC94A04AFG/AFDG
4.3 Self-Boot Operation
Self-boot operation supports two modes: one for use at reset and for setting the microcontroller.
4.3.1 Self-Boot Operation at Reset
To enter this mode, set the RST pin to High or send initialized command. The 2048 fs period (46.4
ms when fs = 44.1 kHz) after a reset release is wait period. The boot operation starts at the end of this
period.
Relationship between fs and Wait Period
fs
32 kHz
44.1 kHz
48 kHz
96 kHz
Wait Period
64.0 ms
46.4 ms
42.7 ms
Boot Time (maximum)
16.0 ms
11.6 ms
10.7 ms
Starting address is fixed to 001h. If the jump address to application to execute at the time of a boot
is specified to be 0001h, at the time of a reset, the initial value of application will be set up
automatically.
When you do not boot at the time of a reset, please set JMP (1FFh: data = 301FFh) as 001h.
4.3.2 Self-Boot Operation When Setting Microcontroller
In this mode, the microcontroller can specify any address and the boot operation starts from that
address.
The BOOT pin can be set to either High or Low. Setting the self-boot ROM start address using the
BOOT command (command: 41h) from the microcontroller starts the boot operation with no wait. The
boot operation when set from the microcontroller is the same as the self-boot operation at reset except
that the boot operation can start from any address.
RST
Boot wait period
2048 fs
Boot period
512 fs (max)
FS
BTMODE
(internal signal)
BootRom Adrs
2
10 11 12 13 14 15 16
3FF
Rom Dt [17:16]
JMP
CMD DT DT DE CMD DE CMD
JMP JMP
BTCSN
BTIFCK
BTIFDI
CDDDCDC
8 clock
DT: Data
DE: DataEnd
C
Figure 3 Boot Timing Chart (at reset)
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2005-09-28