TC94A04AFG Datasheet, PDF (11/42 Pages) Toshiba Semiconductor – 1 chip Audio Digital Processor

2.2 I²C Bus Mode
TC94A04AFG/AFDG
When I2CS = “H”, data can be transmitted or received in I²C bus mode.
When the CS signal is Low, control from the microcontroller is enabled.
In I²C mode, the CS signal can be used fixed to “L”. The IFCK signal is the transmit/receive clock.
The IFDI signal is the data.
The TC94A04AFG/AFDG loads the IFDI data on the IFCK signal rising edge.
When CS = “H”, IFCK and IFD signal are don't care.
2.2.1 Setting Registers
start 32h HZ
CS
HZ
HZ
HZ end
IFCK
IFDI
(MCU →)
A7 A5 A3 A1
A6 A4 A2 A0
C7 C5 C3 C1
C6 C4 C2 C0
D15 D13 D11 D9
D14 D12 D10 D8
D7 D5 D3
D6 D4 D2
An: I²C address
Cn: COMMAND
Dn: Data
The registers are set by command data using the IFDI signal.
The first byte after the I²C address (= 32h) is a command, which differs for each register. The data
sent after that are fixed to two bytes. Both command and data are sent starting from the MSB in I²C
format.
The data loaded internally every two bytes. Note that commands or data that must be switched on
the SYNC signal, such as the RUN command (command-44h) or the IFF flag (command-4Ah), must be
synchronized with the SYNC signal and loaded on that signal.
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2005-09-28