TC94A04AFG Datasheet, PDF (13/42 Pages) Toshiba Semiconductor – 1 chip Audio Digital Processor

2.2.3 Setting RAM (ACMP mode)
TC94A04AFG/AFDG
start 32h HZ
CS
HZ
HZ
HZ
HZ HZ end
IFCK
IFDI
(MCU →)
A7 A5 A3 A1
A6 A4 A2 A0
C7 C5 C3 C1
C6 C4 C2 C0
RA15 RA13 RA11 RA9
RA14 RA12 RA10 RA8
RA7 RA5 RA3 RA1
D15 D13 D11 D9
RA6 RA4 RA2 RA0
D14 D12 D10 D8
Cn: COMMAND
An: I²C address
RAn: RAM-ADDRESS
Dn: Data
In ACMP mode, the TC94A04AFG/AFDG does not write data directly to coefficient RAM (CRAM) or offset RAM (OFRAM). In this mode, data must be written
to the interface buffer RAM (IFB-RAM). Then, all the data are updated together in a period of 1 fs.
For example, if a signal flow filter is designed as in the following diagram, unless the K1 to K5 data are batch-updated, the circuit may resonate. The same
applies to the K6 to K10 data.
Using ACMP mode can reduce the noise caused by updating coefficients while the TC94A04AFG/AFDG is operating.
IFB-RAM is 32-word memory. Therefore, data can be updated at one time in units of up to 32-words.
The length of the data field is 2 × n bytes, where n ^<= 32.
In addition, operation at the time of transmitting other commands, before package rewriting of the data by ACMP mode was completed cannot be guaranteed.
Please set up again after initializing by RST terminal or the initialization command.
K1
+
K2
K4
K6
+
K7
K9
MCU-I/F
IFB-RAM
CRAM
K3
K5
K8 K10
Write one by one･･･
Update for 1 fs
13
2005-09-28