TC94A04AFG Datasheet, PDF (15/42 Pages) Toshiba Semiconductor – 1 chip Audio Digital Processor

TC94A04AFG/AFDG
3.2 Control Commands Description
Each command explanation is shown below. *mark in each command explanation table shows the
initial value at the time of reset.
Command-40h (0100 0000): TIMING (4400h*)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
SYPD SYD1 SYD0
0
SYPA SYA1 SYA0
0
SYPS SYS1 SYS0
0
ELROS
EBC-
OS1
EBC-
OS0
Bit
Name
Description
Value
Operation
D15
⎯
Fixed to 0 (zero)
⎯
⎯
D14
SYPD
ASP digital block sync polarity
switching
0 ASP program starts on falling edge
1* ASP program starts on rising edge
0* Signal after SYNC 1 fs output
D13
SYD
ASP digital block SYNC signal ^{1 Signal after SYNC 2 fs output 2 fs (for 96 kHz sampling)}
D12
[1:0]
input switching
2 SYNC pin
3 ELRI/O pin
D11
⎯
Fixed to 0 (zero)
⎯
⎯
D10
SYPA
DF block sync polarity
switching
0 DF-processing starts in a falling
1* DF-processing starts in a rising
0* SYNC 1 fs output
D9
SYA
1 SYNC 2 fs output
DF block sync input switching
D8
[1:0]
2 Reserved
3 Reserved
D7
⎯
Fixed to 0 (zero)
⎯
⎯
SYNC circuit input polarity
0* Reference input = L Lch
D6
SYPS switching (SYNC reference
signal)
1 Reference input = H Lch
0* Internal divided results
D5
SYS
SYNC circuit input switching
1 SYNC pin
D4
[1:0]
(SYNC reference signal)
2 ELRI/O pin
3 Output ELRI/O pin input divided by 2 (for 96 kHz sampling)
D3
⎯
Fixed to 0 (zero)
⎯
⎯
D2
ELROS
Select the clock at the time of
ELRI/O output
0* 1 fs (Internal fs)
1 2 fs (Internal fs × 2)
0* 32 fs (Internal fs × 32)
D1
EBCOS _{Select the clock at the time of}
1 64 fs (Internal fs × 64)
D0
[1:0]
EBCI/O output
2 128 fs (Internal fs × 128)
3 Reserved
15
2005-09-28