TC94A04AFG Datasheet, PDF (19/42 Pages) Toshiba Semiconductor – 1 chip Audio Digital Processor

TC94A04AFG/AFDG
Command-45h (0100 0101): MSEQ
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
0
0
0
0
0
0 MSA2 MSA1 MSA0
Bit
Name
Description
Value
Operation
D15
to
⎯
Fixed to 0 (zero)
⎯
⎯
D3
D2
to
D0
MSA
[2:0]
Module sequential RAM first
address
0h
to The address of the head to write in is set up.
7h
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
MSEQ MSEQ MSEQ MSEQ MSEQ MSEQ MSEQ MSEQ MSEQ MSEQ
9
8
7
6
5
4
3
2
1
0
Bit
Name
Description
Value
Operation
D15
to
⎯
Fixed to 0 (zero)
⎯
⎯
D10
D9
MSEQ
000h
to
Module sequential RAM data
to The data written in module sequence RAM are set up.
D0
[9:0]
3FFh
Data are sent continuously after transmitting the module sequence RAM head address (2 bytes).
Enable a sequential write to RAM.
45h-MSEQ RAM address (2 bytes)-data (2 bytes)-data (2 bytes)-･････････- data (2 bytes)
(module sequential RAM: 8 words)
19
2005-09-28