TC94A04AFG Datasheet, PDF (16/42 Pages) Toshiba Semiconductor – 1 chip Audio Digital Processor

TC94A04AFG/AFDG
Command-41h (0100 0001): BOOT (0000h*)
D15 D14 D13 D12 D11 D10
0
0
0
0
0
0
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 BTA8 BTA7 BTA6 BTA5 BTA4 BTA3 BTA2 BTA1 BTA0
Bit
Name
Description
Value
Operation
D15
to
⎯
Fixed to 0 (zero)
⎯
⎯
D7
D8
BTA
000h
to
Self-boot ROM start address
to Starts self-boot operation from specified address
D0
[8:0]
1FEh
Command-42h (0100 0010): DIN/AIN (0100h*)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CHSI CHSI
1
0
VS AUTO AIS4 AIS3 AIS2 AIS1 ZDE
SIS ISLT1 ISLT0 IBCS1 IBCS0 IFMT1 IFMT0
Bit
Name
Description
Value
Operation
0* Analog 2 ch input
D15
CHSI
Serial input (SI) switching
D14
[1:0]
1 Digital 4 ch input (2 ch input by the program is possible)
2 Digital 6 ch input
3 Analog and Digital MIX mode
Switching threshold of input
0* CMOS level
pin
D13
VS
[SYNC，ELRI/O，EBCI/O，
1 TTL level
DIN2，DIN1，DIN0]
D12
AUTO Auto mute (analog input)
0* Mute OFF
1 Mute ON
D11
D10
AIS
Switching analog input
D9
[4:1]
D8
AIS4: LIN4/RIN4 pin, AIS3: LIN3/RIN3 pin,
0 to _{AIS2: LIN2/RIN2 pin, AIS1: LIN1/RIN1 pin}
Fh
Select channel, it was set as “1”. (output from OUTL/OUTR)
(1*)
MIX between channels is also possible.
D7
ZDE
Digital-input zero-level
detection mute function
0* Mute OFF
1 Mute ON
D6
SIS
Serial input
0*
Master (synchronizes with internal clock (output from ELRI/O，
EBCI/O pin))
1
Slave (synchronizes with external clock (input from ELRI/O，
EBCI/O pin))
0* 16 slots (bit clock = 32 fs)
D5
ISLT
1 20 slots (bit clock = 40 fs)
Number of serial input slots
D4
[1:0]
2 24 slots (bit clock = 48 fs)
3 32 slots (bit clock = 64 fs)
0* 16 bits
D3
IBCS
Serial input bit length
D2
[1:0]
1 18 bits
2 20 bits
3 24 bits
0* Pads from the beginning
D1
IFMT
Serial input format
D0
[1:0]
1 Pads from the end
2
I2S format
3
16
2005-09-28