TC94A04AFG Datasheet, PDF (12/42 Pages) Toshiba Semiconductor – 1 chip Audio Digital Processor

2.2.2 Setting RAM (sequential)
TC94A04AFG/AFDG
start 32h HZ
CS
HZ
HZ
HZ
HZ
end
IFCK
IFDI
(MCU →)
A7 A5 A3 A1
A6 A4 A2 A0
C7 C5 C3 C1
C6 C4 C2 C0
RA15 RA13 RA11 RA9
RA14 RA12 RA10 RA8
RA7 RA5 RA3 RA1
D15 D13 D11 D9
RA6 RA4 RA2 RA0
D14 D12 D10 D8
Cn: COMMAND
An: I²C address
RAn: RAM-ADDRESS
Dn: Data
The RAMs are set by command data using the IFDI signal.
The first byte after the I²C address (32h) is a command, which differs for each RAM. The next two bytes contain the start address for each RAM.
The length of the data field following the RAM address bytes is 2 × n bytes. The address is automatically incremented by 1.
During program running, 1 word of data is written at a time in internal RAM synchronizing with a SYNC signal.
Therefore, when performing continuously two or more write to word, unless it applies more than 1/fs [sec] per 1 word and it sets up, taking in of data is not
performed correctly.
At the time of program STOP, it is written in asynchronous.
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2005-09-28