TL16PC564BLVI_16 Datasheet, PDF (8/35 Pages) Texas Instruments – PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER

TL16PC564BLVI
Not Recommended For New Designs
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS627− SEPTEMBER 2004
subsystem memory map
The subsystem attribute memory space is mapped as follows:
Subsystem Address Bits 8 −0
0 − 255
256
257
258
259
260
261
262
263
Attribute Memory Space
CIS
CCR0
CCR1
CCR2
CCR3
CCR4
CCR5
CCR6
CCR7
The subsystem control space is mapped as follows:
Subsystem Address Bits 8 −0
272
288
Control Space
Control Register
PGMCLK Register (write only)
The subsystem UART space is mapped as follows:
Subsystem Address Bits 8 −0
304
304
305
306
307
308
309
310
311
320
320
† _{Only when serial bypass mode is enabled}
UART Space
UART MCR bit 5 (write only)
UART DLL (read only)
UART IER (read only)
UART FCR (read only)
UART LCR (read only)
UART MCR (read only)
UART LSR (read only)
UART MSR (read only)
UART DLM (read only)
UART transmitter FIFO (read only)^†
UART receiver FIFO (write only)^†
host CPU/attribute-memory interface
The host CPU/attribute-memory interface is comprised of one port of the internal DPRAM, the eight CCRs, and
necessary control circuitry. Signals HA0 and CE1 are gated together internally so that the output of the gate is
low when both signals have been asserted by the host CPU. This output is combined with REG and the decoded
address, HA(9−1), to provide the chip enable for the DPRAM and CCRs. This composite chip enable in
combination with WE or OE allows writes and reads to the DPRAM and CCRs.
subsystem/attribute-memory interface
The subsystem/attribute-memory interface is comprised of the second port of the internal DPRAM, the eight
CCRs, and necessary control circuitry. When in multiplexed mode (SSAB = 0), the combination of signals
SELZ/I and ALE(AS) allows either a positive-pulse Intel or a negative-pulse Zilog address latch-enable strobe
to latch the address on SA8 and SAD(7−0). When in the Zilog mode (SELZ/I high), the combination of read/write
[WR(R/W)], data strobe [RD(DS)], and decoded address allows ZBUS access. When in the Intel configuration
(SELZ/I low), the combination of read [RD(DS)], write [WR(R/W)], and decoded address allows IBUS access.
When in nonmultiplexed mode (SSAB = 1), SA(7−0) become the lower-order address bits, SAD(7−0) are strictly
the bidirectional data bus, and ALE(AS) is nonfunctional. All other interface signals function the same.
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