TL16PC564BLVI_16 Datasheet, PDF (11/35 Pages) Texas Instruments – PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER

Not Recommended For New Designs
TL16PC564BLVI
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS627− SEPTEMBER 2004
subsystem control register
The subsystem control register is an 8-bit register located at subsystem address 110 (hex). This register is
programmed based on host CPU configuration information and has a default selection of COM2 after a valid
reset. The bit definitions are as follows (0 = LSB):
Bits 0 and 1 define which host COM port the UART is connected to when the chip is in the address mode.
COM2 is the default (power-up) condition.
BIT 1
0
1
0
1
BIT 0
0
0
1
1
COM PORT
COM1
COM2
COM3
COM4
Bit 2 is a host CPU interrupt-enable bit. When bit 2 is set, any subsystem attribute-memory write cycle
causes STSCHG to be asserted. Bit 2 is cleared after a valid reset.
Bit 3 enables or disables address-mode selection as described in the host CPU/UART interface description.
Bit 3 is cleared (disabling the address mode) after a valid reset.
Bits 4 and 5 together ensure adherence to PCMCIA power-up requirements. At power up, the card must
operate as a memory card and all host CPU I/O operations must be disabled. IREQ, which doubles as the
host CPU READY/BUSY line, powers up low, indicating that the memory card is busy. Once the subsystem
initializes attribute memory, the subsystem sets bit 4 to indicate that the memory card is ready. Then bit 5 is
reset, changing the configuration from a memory card to an I/O card, enabling host CPU UART accesses.
IREQ now becomes the host CPU interrupt-request line.
BIT 5
1
1
0
BIT 4
0
1
X
CONFIGURATION
Memory card, I/O operation (UART) disabled; IREQ is low, indicating card is busy (power-up and reset
condition)
Memory card, I/O operation (UART) disabled; IREQ is high, indicating card is ready
I/O card, I/O operation (UART) enabled; IREQ now functions as the host CPU interrupt-request line
Bit 6 is a self-clearing bit that resets the subsystem IRQ signal. Writing a 1 to this location clears the IRQ
interrupt.
Bit 7 enables or disables serial-bypass mode as described in the subsystem serial-bypass-mode
description. Bit 7 is cleared (disabling serial-bypass mode) after a valid reset.
subsystem PGMCLK register/divide-by-n circuit
The subsystem PGMCLK register is a 6-bit write-only register located at address 120 hex and is used to select
the divisor of the divide-by-n-and-a-half circuitry. Any write to this register generates a reset to the UART and
the divide-by-n circuitry.
The divide-by-n circuitry allows for a divisor from 0 to 31.5 in 0.5 increments (PGMCLK0 is the half bit). The
divided clock output drives the UART clock input and can be seen on UARTCLK. The UART requires a clock
with a minimum high pulse duration of 50 ns and a minimum low pulse duration of 50 ns (10-MHz maximum
operating frequency). A programmed divisor between 2 and 7.5 drives the UART clock low for one XIN clock
cycle for integer divisors and one-and-a-half XIN clock cycles for integer-plus-a-half divisors. A programmed
divisor of eight or greater drives the UART clock low for four XIN clock cycles for integer divisors. A
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