TL16PC564BLVI_16 Datasheet, PDF (18/35 Pages) Texas Instruments – PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER

TL16PC564BLVI
Not Recommended For New Designs
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS627− SEPTEMBER 2004
subsystem Intel-mode timing requirements (32 MHz) (see Figure 10)
INTEL
SYMBOL
tLHLL
tAVLL
tPLLL
tLLAX
tLLWL
tLLRL
tWHLH
tAFRL
tRLRH
tWLWH
tRHAX
tWHDX
tWHPH
tRHPH
tPHPL
JEDEC
SYMBOL
tw11
tsu16
td25
th15
td26
td27
td28
td29
tw12
tw13
td30
th16
td31
td32
tw14
Pulse duration, ALE high
Setup time, SA8, SAD(7 −0) valid to ALE low
Delay time, CS low to ALE low
Hold time, SA8, SAD(7 −0) valid after ALE↓
Delay time, ALE low to WR low
Delay time, ALE low to RD low
Delay time, WR high to ALE high
Delay time, SA8, SAD(7 −0) in high-impedance state to RD low
Pulse duration, RD low
Pulse duration, WR low
Delay time, RD high to SA8, SAD(7 −0) active
Hold time, SA8, SAD(7 −0) valid after WR high
Delay time, WR high to CS high
Delay time, RD high to CS high
Pulse duration, CS high
subsystem Zilog-mode timing requirements (20 MHz) (see Figure 11)
ZILOG
SYMBOL
tdA(AS)
tdAS(A)
tdAS(DR)
twAS
tdA(DS)
twDS(read)
twDS(write)
tdDS(DR)
thDS(DR)
tdDS(A)
tdDS(AS)
tdDO(DS)
tdRW(AS)
JEDEC
SYMBOL
tsu17
td33
td34
tw15
td35
tw16
tw17
td36
th17
th18
td37
td38
td39
Setup time, SA8 and SAD(7 −0) valid before AS high
Delay time, AS high to SA8 and SAD(7 −0) invalid
Delay time, AS high to data in on SAD(7 −0)
Pulse duration, AS low
Delay time, SA8 and SAD(7 −0) invalid to DS low
Pulse duration, DS low (read)
Pulse duration, DS low (write)
Delay time, DS low to data in valid
Hold time, DS high to data in invalid
Hold time, DS high to data out invalid
Delay time, DS high to AS low
Delay time, SAD(7 −0) (write data from µP) valid to DS low
Delay time, R/W active to AS high
MIN MAX UNIT
48
ns
21
ns
21
ns
21
ns
16
ns
16
ns
21
ns
0
ns
120
ns
120
ns
48
ns
48
ns
21
ns
21
ns
21
ns
MIN MAX UNIT
20
ns
35
ns
150 ns
35
ns
0
ns
125
ns
65
ns
80 ns
0
ns
20
ns
30
ns
10
ns
20
ns
18
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