TL16PC564BLVI_16 Datasheet, PDF (21/35 Pages) Texas Instruments – PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER

Not Recommended For New Designs
TL16PC564BLVI
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS627− SEPTEMBER 2004
host CPU status change timing requirements over recommended ranges of operating free-air
temperature and supply voltage (see Figure 17)
td54 Delay time, subsystem write↑ to STSCHG↓ (see Note 14)
td55 Delay time, OE↓ to STSCHG high impedance (see Note 15)
NOTES: 15. Synchronized to rising edge of ARBCLKI
16. Synchronized to falling edge of ARBCLKI
MIN MAX UNIT
2tc5
3tc5
ARBCLKI
cycles
tc5
2tc5
ARBCLKI
cycles
PARAMETER MEASUREMENT INFORMATION
N
tw1
tc1
XIN
tw2
td1
td2
UARTCLK
(1/0.5 − 1/1.5)
td3
UARTCLK†
(1/2 − 1/7)
1 XIN Cycle
td3
UARTCLK†
(1/2.5 − 1/7.5)
1.5 XIN Cycles
td3
UARTCLK‡
(1/8 − 1/31)
td4
(N −1)XIN Cycles
td5
(N −1.5)XIN Cycles
td4
td3
UARTCLK‡
(1/8.5 − 1/31.5)
4 XIN Cycles
4.5 XIN Cycles
(N −4)XIN Cycles
td5
(N −4.5)
XIN Cycles
† _{The low portion of the UARTCLK cycle = 1 XIN cycle for PGMCLK integer values of 2 to 7 and 1.5 XIN cycles for PGMCLK noninteger values}
2.5 to 7.5.
‡ _{The low portion of the UARTCLK cycle = 4 XIN cycles for PGMCLK integer values of 8 to 31 and 4.5 XIN cycles for PGMCLK noninteger values}
8.5 to 31.5.
Figure 1. XIN Clock Timing Waveforms
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