TL16PC564BLVI_16 Datasheet, PDF (6/35 Pages) Texas Instruments – PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER

TL16PC564BLVI
Not Recommended For New Designs
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS627− SEPTEMBER 2004
Terminal Functions
TERMINAL
NAME
PZ NO.
INTER-
FACE†
I/O
DESCRIPTION
RI
50
U
I Ring indicator. RI is an active-low modem status signal whose condition can be checked by
reading bit 6 (RI) of the MSR. The trailing-edge ring indicator (TERI) bit 2 of the MSR indicates
that RI has transitioned from a low to a high state since the last read from the MSR. If the modem
status interrupt is enabled when this transition occurs, an interrupt is generated.
RST
11
M
O This is the qualified active-low reset signal. RST has a fail-safe open-drain output.
RTS
35
U
O Request to send is an active-low signal. When active, RTS informs the modem of the data set
that the UART is ready to receive data. RTS is set to its active state by setting the RTS modem
control register bit and is set to its inactive (high) state either as a result of a reset, doing
loop-mode operation, or by resetting bit 1 (RTS) of the MCR.
SA0
53
S
I When SSAB is high, this is the subsystem address bus and SAD (7− 0) is the subsystem data
SA1
55
bus. When SSAB is low, this bus is not used and SAD(7− 0) is the subsystem multiplexed
SA2
56
address/data bus.
SA3
57
SA4
58
SA5
59
SA6
61
SA7
65
SA8
24
S
I Address bit 8 is bit 8 of the subsystem address bus.
SAD0
SAD1
SAD2
SAD3
SAD4
SAD5
SAD6
SAD7
25
S
I/O Subsystem address/data 7 −0. This is a multiplexed bidirectional address/data bus to the
23
attribute-memory DPRAM and CCRs when SSAB is low. This becomes a bidirectional data bus
20
when SSAB is high.
19
18
17
15
14
SELZ / I
28
S
I Select Zilog or Intel mode. SELZ / I is used to select between a Zilog-like or Intel-like
microcontroller. 1 = Zilog, 0 = Intel.
SIN
33
U
I Serial data input. SIN moves information from the communication line or modem to the
TL16PC564BLVI UART receiver circuits. Data on the serial bus is disabled when operating in
the loop mode.
SOUT
45
U
O Serial out. SOUT is the composite serial data output to a connected communication device.
SOUT is set to the marking (logic 1) state as a result of a reset.
SSAB
3
S
I Separate subsystem address bus. SSAB is used to select between a multiplexed address/data
bus subsystem interface (SSAB = 0) and a subsystem interface with separate address and data
buses (SSAB = 1). This signal has an internal pulldown resistor.
STSCHG
74
H
O Status change. STSCHG is an optional active-low output signal used to alert the host that a
subsystem write to attribute memory has occurred. This signal has an open-drain output.
TESTOUT
70
M
O This is a production test output.
UARTCLK
51
M
O UART clock. UARTCLK is a clock output whose frequency is determined by the frequency on
XIN and the divisor value on the PGMCLK register.
VCC
10,21, 22, 36, M
47,52, 60,
3.3-V or 5-V supply voltage
72, 86, 97
† _{Host = H, Subsystem = S, UART = U, Miscellaneous = M}
6
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