TL16PC564BLVI_16 Datasheet, PDF (20/35 Pages) Texas Instruments – PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER

TL16PC564BLVI
Not Recommended For New Designs
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS627− SEPTEMBER 2004
ARBCLK switching characteristics over recommended operating free-air temperature range (see
Figure 14)
TEST CONDITIONS
MIN
tc4 Cycle time, internal arbitration clock ( ARBCLKI ÷ ARBPGM)
VCC = 3.3 V,
VCC = 5 V
See Note 11
26
14
tc5 Cycle time, arbitration clock
VCC = 3.3 V,
See Note 11
26
VCC = 5 V
14
td42 Delay time, ARBCLKI↑ to ARBCLK0↑ (÷ 1)
VCC = 3.3 V,
VCC = 5 V
See Note 11
td43 Delay time, ARBCLKI↓ to ARBCLK0↓ (÷ 1)
VCC = 3.3 V,
VCC = 5 V
See Note 11
td44 Delay time, ARBCLKI↑ to ARBCLK0↑ (÷ 2)
VCC = 3.3 V,
VCC = 5 V
See Note 11
td45 Delay time, ARBCLKI↑ to ARBCLK0↓ (÷ 2)
VCC = 3.3 V,
VCC = 5 V
See Note 11
td46 Delay time, ARBCLKI↑ to ARBCLK0↑ (÷ 4)
VCC = 3.3 V,
VCC = 5 V
See Note 11
td47 Delay time, ARBCLKI↑ to ARBCLK0↓ (÷ 4)
VCC = 3.3 V,
VCC = 5 V
See Note 11
td48 Delay time, ARBCLKI↑ to ARBCLK0↑ (÷ 8)
VCC = 3.3 V,
VCC = 5 V
See Note 11
td49 Delay time, ARBCLKI↑ to ARBCLK0↓ (÷ 8)
VCC = 3.3 V,
VCC = 5 V
See Note 11
NOTES: 11. TL16PC564BLVI device tested at 3 V.
14. tc4 MAX = N/6, where N = shortest (in ns) of the two attribute-memory accesses, host CPU or subsystem.
MAX
Note 14
Note 14
13
7.3
15.5
10
15.3
8.8
17.5
11
19.5
11.5
21.5
13.5
22.7
13.5
25
15.7
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
reset timing requirements over recommended ranges of operating free-air temperature and supply
voltage (unless otherwise noted) (see Figure 15)
tw22 Pulse duration, RESET active
tw23 Pulse duration, RESET inactive
td50 Delay time, ARBCLKI↑ to RST low
td51 Delay time, ARBCLKI↑ to RST high impedance
NOTE 11: TL16PC564BLVI device tested at 3 V.
TEST CONDITIONS
VCC = 3.3 V,
VCC = 5 V
VCC = 3.3 V,
VCC = 5 V
See Note 11
See Note 11
MIN
8⋅tc5
8⋅tc5
MAX
10.4
7.5
13.9
9.7
UNIT
ns
ns
ns
ns
subsystem interrupt-request timing requirements over recommended ranges of operating free-air
temperature and supply voltage (see Figure 16)
td52 Delay time, WE↑ to IRQ↑ (see Note 15)
td53 Delay time, SCR bit 6↑ to IRQ↓ (see Note 16)
NOTES: 11. TL16PC564BLVI device tested at 3 V.
15. Synchronized to rising edge of ARBCLKI
16. Synchronized to falling edge of ARBCLKI
MIN MAX UNIT
2tc5
3tc5
ARBCLKI
cycles
tc5
2tc5
ARBCLKI
cycles
20
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