TL16PC564BLVI_16 Datasheet, PDF (19/35 Pages) Texas Instruments – PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER

Not Recommended For New Designs
TL16PC564BLVI
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
subsystem Intel nonmultiplexed timing requirements (see Figure 12)
tsu18
tw18
tw19
tsu19
ten4
td40
th19
th20
tdis3
Setup time, SA(8 −0), CS valid to RD, WR↓
Pulse duration, RD low
Pulse duration, WR low
Setup time, SAD(7 −0) valid to WR↑
Enable time, RD↓ to SAD(7 −0) driving
Delay time, RD↓ to SAD(7 −0) valid
Hold time, SA(8 −0), CS valid after RD, WR↑
Hold time, SAD(7 −0) valid after WR↑
Disable time, RD↑ to SAD(7 −0) high impedance
SLLS627− SEPTEMBER 2004
MIN MAX UNIT
30
ns
120
ns
120
ns
50
ns
5
ns
105 ns
30
ns
30
ns
5
15 ns
subsystem Zilog nonmultiplexed timing requirments (see Figure 13)
tsu20
tsu21
tw20
tw21
tsu22
ten5
td41
th21
th22
tdis4
Setup time, SA(8 −0), CS, R/W valid to DS↓ (write)
Setup time, SA(8 −0), CS, R/W valid to DS↓ (read)
Pulse duration, DS low (write)
Pulse duration, DS low (read)
Setup time, SAD(7 −0) valid to DS↑
Enable time, DS↓ to SAD(7 −0) driving
Delay time, DS↓ to SAD(7 −0) valid
Hold time, SA(8 −0), CS, R/W valid after DS↑
Hold time, SAD(7 −0), CS, R/W valid after DS↑
Hold time, DS↑ to SAD(7 −0) high impedance
MIN MAX UNIT
90
ns
30
ns
65
ns
125
ns
50
ns
5
ns
105 ns
30
ns
30
ns
5
15 ns
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