TL16PC564BLVI_16 Datasheet, PDF (26/35 Pages) Texas Instruments – PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER

TL16PC564BLVI
Not Recommended For New Designs
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS627− SEPTEMBER 2004
PARAMETER MEASUREMENT INFORMATION
tc2
HA(9 −0)
tsu10
90%
10%
CE1, CE2
90%
10%
tsu8
10%
90%
trec1
10%
90%
ÎÎÎÎÎÎÎÎÎÎÎÎ ^{WE See Note A}
HD(7 −0)
See Note C
See Note B
90%
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _10%
See Note A
tsu12
th9
90%
10%
Data Input Established
90%
10%
NOTES: A. The hatched portion may be either high (H) or low (L).
B. OE must be high (H).
C. When the data I/O terminal is in the output state, no signals should be applied to HD(7 −0) by the system.
Figure 8. Host CPU Attribute-Memory Write Timing Waveforms (CE Control)
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