TL16PC564BLVI_16 Datasheet, PDF (7/35 Pages) Texas Instruments – PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER

Not Recommended For New Designs
TL16PC564BLVI
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS627− SEPTEMBER 2004
Terminal Functions
TERMINAL
NAME
PZ NO.
WE
89
INTER-
FACE†
I/O
DESCRIPTION
H
I Write enable. WE is an active-low input signal used for strobing attribute-memory write data into
the card. This signal has an internal pullup resistor
WR(R/W)
31
S
I Write or read/write enable. WR(R/W) is the active-low write enable in the Intel mode and read/write
in the Zilog mode.
XIN
42
M
I Crystal input. XIN is a clock input divided internally based on the PGMCLK register value, then
used as the primary UART clock input.
VTEST
2
M
I VTEST is an active-high production test input with an internal pulldown resistor. It can be left open
or tied to ground.
† _{Host = H, Subsystem = S, UART = U, Miscellaneous = M}
detailed description
reset-validation circuit
A reset-validation circuit has been implemented to qualify the active-high RESET input. At power up, the level
on the RST output is unknown. Whenever RESET is stable for at least eight ARBCLKIs, RST reflects the
inverted state of that stable value of RESET. Any changes on RESET must be valid for eight ARBCLKI clocks
before the change is reflected on RST. This 8-clock filter provides needed hysteresis on the master reset input.
RST is driven by a low-noise, open-drain, fail-safe output buffer.
host CPU memory map
The host CPU attribute memory space is mapped as follows:
Host CPU Address Bits 9−1 (HA0 = 0)
0 − 255
256
257
258
259
260
261
262
263
Attribute Memory Space
CIS
CCR0
CCR1
CCR2
CCR3
CCR4
CCR5
CCR6
CCR7
The host CPU I/O space is mapped as follows:
Normal Mode
0 (DLAB = 0)^†
0 (DLAB = 0)^†
0 (DLAB = 1)^†
1 (DLAB = 0)^†
1 (DLAB = 1)^†
2
3
4
5
6
7
Address Mode (hex)
COM1 COM2 COM3 COM4
3F8 2F8 3E8 2E8
3F8 2F8 3E8 2E8
3F8 2F8 3E8 2E8
3F9 2F9 3E9 2E9
3F9 2F9 3E9 2E9
A 3EA 2EA
3FA 2FA 3EA 2EA
3FB 2FB 3EB 2EB
3FC 2FC 3EC 2EC
3FD 2FD 3ED 2ED
3FE 2FE 3EE 2EE
3FF 2FF 3EF 2EF
I/O Space
UART receiver buffer register (RBR) − read only
UART transmitter holding register (THR) − write only
UART divisor latch LSB (DLL)
UART interrupt enable register (IER)
UART divisor latch MSB (DLM)
UART interrupt identification register (IIR) − read only
UART FIFO control register (FCR) − write only
UART line control register (LCR)
UART modem control register (MCR) − bit 5 read only
UART line status register (LSR)
UART modem status rgister (MSR)
UART scratch register (SCR)
† _{DLAB is bit 7 of the line control register (LCR).}
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