TL16PC564BLVI_16 Datasheet, PDF (3/35 Pages) Texas Instruments – PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER

Not Recommended For New Designs
TL16PC564BLVI
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
block diagram
95, 96, 98 −100, 75 −77
HD7 −HD0†
92, 90, 87, 85 −81,
HA9 −HA0† ^{79, 78}
10
REG ⁷³
94
CE1
CE2 ⁶²
WE ⁸⁹
93
OE
63
IORD
8
10
Host CPU
Control
Logic
Reset
Control
5
ARBCLKI
ARBPGM1 − ^9,8
2
ARBPGM0†
14, 15, 17 −20,
SAD7 −SAD0† ^{23, 25}
8
24,65,61,
SA8−SA0 ^{59 −55,53}
28
SELZ / I ₃
SSAB ₂₆
ALE(AS)
WR(R/W) ³¹
29
RD(DS)
32
CS
8
9
Subsystem
Control
Logic
Reset
67
RESET
64
IOWR ₁
EXTEND
XIN ⁴²
SIN ³³
40
RCLK
CTS ⁴⁹
48
DCD
46
DSR
RI ⁵⁰
† _{Bit 0 is the least significant bit.}
Reset
Validation
6
Divide by N
Reset
SLLS627− SEPTEMBER 2004
10
8
DATA
ADDR
OE
WE
Reset
Attribute
Memory
(CIS 256 × 8,
CCR 8 × 8
plus arbitration
logic)
DATA
9
ADDR
OE
WE
7 _ARBCLKO
71 _INPACK
74 _STSCHG
27 _IRQ
88 _IREQ
51 _UARTCLK
11 _RST
UART
TL16C550C
UART Select
Master Clock
Reset
38 _BAUDOUT
34 _DTR
37 _OUT1
44 _OUT2
35 _RTS
45 _SOUT
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