LMH0031 Datasheet, PDF (8/39 Pages) National Semiconductor (TI) – SMPTE 292M/259M Digital Video Deserializer Descrambler with Video and Ancillary Data FIFOs

LMH0031
SNLS218A – JANUARY 2006 – REVISED APRIL 2013
AC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified⁽¹⁾.
Symbol
Parameter
Conditions
Reference
Min
Serial Video Data Inputs
SMPTE 259M, Level C
SMPTE 259M, Level D
BR_SDI
Serial Input Data Rate
SMPTE 344M
SMPTE 292M
SMPTE 292M
SDI, SDI
20%–80%, SMPTE 259M
Data Rates
0.4
t_r, t_f
Rise Time, Fall Time
20%–80%, SMPTE 292M
Data Rates
Parallel Video Data Outputs
f_VCLK
t_pd
Video Output Clock
Frequency
Propagation Delay, Video
Clock to Video Data Valid
SMPTE 259M, 270M_BPS
SMPTE 267M, 360M_BPS
SMPTE 344M, 540M_BPS
SMPTE 292M, 1,483M_BPS
SMPTE 292M, 1,485M_BPS
50%–50%
V_CLK
V_CLK to DV_N
Timing Diagram
DC_V
Duty Cycle, Video Clock
27MHz
V_CLK
t_JIT
Video Data Output Clock
Jitter
36MHz
54MHz
V_CLK
74.25MHz
Parallel Ancillary / Control Data Inputs, Multi-function Parallel Bus Inputs
f_ACLK
Ancillary / Control Data Clock
Frequency
DC_A
Duty Cycle, Ancillary Data
Clock
ANC Data clock ⁽²⁾
A_CLK
45
t_r, t_f
Output Rise Time, Fall Time 10%–90%
1.0
t_S
Setup Time, AD_N to A_CLK or
IO_N to A_CLK Rising Edge
Control Data Input or I/O Bus
IO_N, AD_N, A_CLK
Timing Diagram
3.0
t_H
Hold Time, Rising Edge A_CLK ^Input
to AD_N or A_CLK to IO_N
3.0
Parallel Ancillary / Control Data Outputs
t_pd
Propagation Delay, Clock to
Control Data
50%–50%
t_pd
Propagation Delay, Clock to
Ancillary Data
A_CLK to AD_N
Timing Diagram
Multi-function Parallel I/O Bus
t_r, t_f
Rise Time, Fall Time
10%–90%
IO0–IO7
Timing Diagram
1.0
PLL/CDR, Format Detect
t_LOCK
Lock Detect Time
SD Rates⁽³⁾
HD Rates⁽³⁾
t_FORMAT
Format Detect Time
All Rates
Typ
270
360
540
1,483
1,485
1.0
27.0
36.0
54.0
74.176
74.25
0.5
50±5
2.0
1.4
1.0
0.5
50
1.5
1.5
1.5
8.5
11.5
1.5
0.32
0.26
20
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Max
Units
M_BPS
1.5
ns
270
ps
MHz
2.0
ns
%
ns_P-P
V_CLK
55
3.0
MHz
%
ns
ns
3.0
ns
1.0
1.0
ms
(1) Typical values are stated for V_DDIO = V_DDSI = +3.3V, V_DDD = V_DDPLL = +2.5V and T_A = +25°C.
(2) When used to clock control data into or from the LMH0031, the duty cycle restriction does not apply.
(3) Measured from rising-edge of first SDI cycle until Lock Detect bit goes high (true). Lock time includes CDR phase acquisition time plus
PLL lock time.
8
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