LMH0031 Datasheet, PDF (13/39 Pages) National Semiconductor (TI) – SMPTE 292M/259M Digital Video Deserializer Descrambler with Video and Ancillary Data FIFOs

LMH0031
www.ti.com
SNLS218A – JANUARY 2006 – REVISED APRIL 2013
Once the PLL attains lock, the video format detector processes the received data to determine the raster
characteristics (video data format) and configure the LMH0031 to handle it. This assures that the parallel output
data will be properly formatted, that the correct data rate is selected and that Ancillary Data and CRC/EDH data
are correctly detected and checked. Supported parallel data formats or sub-formats may belong to any one of
several component standards: SMPTE 125M, SMPTE 267M, SMPTE 260M, 274M, 295M or 296M. Refer to
Table 4 for the supported formats. (See also the Application Information section for handling of other raster
formats or format extensions developed after this device was designed). The detected video standard information
is passed to the device control system and saved in the control registers from whence it may be read by the
user.
The LMH0031 may be configured to operate in a single video format by loading the appropriate FORMAT
SET[4:0] control data into the FORMAT 0 control register. Also, the LMH0031 may be configured to handle only
the standard-definition data formats by setting the SD ONLY bit or only the high-definition data formats by setting
the HD ONLY bit in the FORMAT 0 control register. When both bits are reset, the default condition, the part
automatically detects the data rate and range.
Aligned and de-processed parallel data passes into a variable-depth video FIFO prior to output. Video FIFO
depth from 0 to 4 registers is set by a 3-bit word written into the VIDEO FIFO Depth[2:0] bits in the ANC 0
control register. The video FIFO permits adjustment of the parallel video data output timing or delay at a parallel
word rate. The occurence of corresponding TRS indicator bits, EAV, SAV and NSP, in the control register
corresponds to the input register position of the FIFO. This positioning permits a look-ahead function in which the
alignment status of the video data can be determined up to four parallel clock periods prior to the appearance of
that data at the parallel data output.
The parallel video data is output on DV[19:0]. The 20-bit parallel video data is organized so that for HDTV data,
the upper-order 10 bits DV[19:10] are luminance (luma) information and the lower 10 bits DV[9:0] are colour
difference (chroma) information. SDTV data use the lower-order 10-bits DV[9:0] for both luma and chroma
information. (The SDTV parallel data is also duplicated on DV[19:10]). V_CLK is the parallel output word rate clock
signal. The frequency of V_CLK is appropriate to either the HD or SD data being processed. Data is valid between
the falling edges of a V_CLK cycle. Data may be clocked into external devices on the rising-edge of V_CLK. The
DV[19:0] and V_CLK signals are LVCMOS-compatible.
ANCILLARY/CONTROL DATA PATH
The 10-bit ancillary and Control Data PortAD[9:0] serves two functions in the LMH0031. Ancillary Data from
the Ancillary Data FIFO is output from this port after its recovery from the video data stream. The utilization and
flow of Ancillary Data from the device is managed by a system of control bits, masks and IDs stored in the
control data registers. This port also provides read/write access to contents of the configuration and control
registers. The signals RD/WR, ANC/CTRL and A_CLK control data flow through the port.
CONTROL DATA FUNCTIONS
Control data is input to and output from the LMH0031 using the lower-order 8 bits AD[7:0] of the
ancillary/Control Data Port. This control data initializes, monitors and controls operation of the LMH0031. The
upper two bits AD[9:8] of the port function as handshaking signals with the device accessing the port. When
either a control register read or write address is being written to the port, AD[9:8] must be driven as 00b (0XXh,
where XX are AD[7:0]). When control data is being written to the port, AD[9:8] must be driven as 11b (3XXh,
where XX are AD[7:0]). When control data is being read from the port, the LMH0031 will output AD[9:8] as 10b
(2XXh, where XX are output data AD[7:0]) and may be ignored by the monitoring system.
NOTE
After either a manual or power-on reset, A_CLK must be toggled three (3) times to complete
initiallization of the Ancillary and Control Data Port.
The sequence of clock and control signals for reading control data from the ancillary/control data port is shown in
Figure 3. Control data read mode is invoked by making the ANC/CTRL input low and the RD/WR input high.
The 8-bit address of the control register set to be accessed is input to the port on bits AD[7:0]. To identify the
data as an address, AD[9:8] must be driven as 00b. The complete address word will be 0XXh, where 0 is
AD[9:8] and XX are AD[7:0]. The address is captured on the rising edge of A_CLK. When control data is being
read from the port, the LMH0031 will output AD[9:8] as 10b (2XXh, where XX are output data AD[7:0]) and may
be ignored by the monitoring system. Data being output from the selected register is driven by the port
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