LMH0031 Datasheet, PDF(18/39 Page) National Semiconductor (TI) – SMPTE 292M/259M Digital Video Deserializer Descrambler with Video and Ancillary Data FIFOs

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LMH0031 Datasheet, PDF (18/39 Pages) National Semiconductor (TI) – SMPTE 292M/259M Digital Video Deserializer Descrambler with Video and Ancillary Data FIFOs

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LMH0031

SNLS218A â JANUARY 2006 â REVISED APRIL 2013

www.ti.com

The LMH0031 indicates that the PLL is locked to the incoming data rate and that the CDR has acquired a phase

of the serial data by setting the Lock Detect bit in the Video Info 0 control register. Indication of the standard

being processed is retained in the FORMAT[4:0] bits in the FORMAT 1 control data register. Format data from

this register can be programmed for output on the multi-function I/O port. The power-on default assigns Lock

Detect as I/O Port bit 4.

POWER SUPPLIES, POWER-ON-RESET AND RESET INPUT

The LMH0031 requires two power supplies, 2.5V for the core logic functions and 3.3V for the I/O functions. The

supplies must be applied to the device in proper sequence. The 3.3V supply must be applied prior to or

coincident with the 2.5V supply. Application of the 2.5V supply must not precede the 3.3V supply. It is

recommended that the 3.3V supply be configured or designed so as to control application of the 2.5V supply in

order to satisfy this sequencing requirement.

The LMH0031 has an automatic, power-on-reset circuit. Reset initializes the device and clears TRS detection

circuitry, all latches, registers, counters and polynomial generators/checkers and resets the EDH/CRC characters

to 00h. An active-HIGH-true, manual reset input is available at pin 49. The reset input has an internal pull-down

device and may be considered inactive when unconnected.

Important: When power is first applied to the device or following a reset, the ancillary and Control Data Port

must be initialized to receive data. This is done by toggling ACLK three times.

TEST PATTERN GENERATOR (TPG) AND BUILT-IN SELF-TEST (BIST)

The LMH0031 includes an on-board, parallel video test pattern generator (TPG). Four test pattern types are

available in both HD and SD formats, NTSC and PAL standards, and 4x3 and 16x9 raster sizes. The test

patterns are: flat-field black, PLL pathological, equalizer (EQ) pathological and a 75%, 8-colour vertical bar

pattern. The pathologicals follow recommendations contained in SMPTE RP 178-1996 regarding the test data

used. The colour bar pattern has optional bandwidth limiting coding in the chroma and luma data transitions

between bars. The VPG FILTER ENABLE bit in the VIDEO INFO 0 control register enables the colour bar filter

function. The test pattern data is available at the video data outputs, DV[19:0] with a corresponding parallel rate

clock, VCLK, appropriate to the particular standard and format selected.

The TPG also functions as a built-in self-test (BIST) which can be used to verify device functionality. The BIST

function performs a comprehensive go/no-go test of the device. The test may be run using any of the HD colour

bar patterns or one of two SD patterns, either the 270 Mb/s NTSC colour bar or the PAL PLL pathological, as the

test data pattern. Data is input from the digital processing block, processed through the device and tested for

errors using either the EDH system for SD or the CRC system for HD. Clock signals from the CDR block supply

timing for the test data. The CDR must be supplied a 27MHz reference clock via the XTALi/Ext Clk input (or

using the internal oscillator and crystal) during the TPG or BIST function. A go/no-go indication is logged in the

Pass/Fail bit of the TEST 0 control register set. This bit may be assigned as an output on the multifunction I/O

port.

TPG and BIST operation is initiated by loading the code for the desired test pattern into the Test Pattern

Select[5:0] bits and by setting the TPG Enable bit of the TEST 0 register. Note that when attempting to use the

TPG or BIST immediately after the device has been reset or powered on, the TPG defaults to the 270Mbps SD

rate. The device must be configured for the desired test pattern by loading the appropriate code in to the TEST 0

configure itself to run at the correct rate and generate valid data. Table 5 gives the available test patterns and

codes.

The Pass/Fail bit in the control register gives the device test status indication. If no errors have been detected,

this bit will be set to logic-1 approximately 2 field intervals after TPG Enable is set. If errors have been detected

in the internal circuitry of the LMH0031, Pass/Fail will remain reset to a logic-0. TPG or BIST operation is

stopped by resetting the TPG Enable bit. Parallel output data is present at the DV[19:0] outputs during TPG or

BIST operation.

Example: Enable the TPG Mode to use the NTSC 270Mbps colour bars as the BIST and TPG pattern. Enable

TPG operation using the I/O port.

1. Set ANC/CTRL to a logic-low.

2. Set RD/WR to a logic-low.

3. Present 00Dh to AD[9:0] as the TEST 0 register address.

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