LMH0031 Datasheet, PDF (32/39 Pages) National Semiconductor (TI) – SMPTE 292M/259M Digital Video Deserializer Descrambler with Video and Ancillary Data FIFOs

LMH0031
SNLS218A – JANUARY 2006 – REVISED APRIL 2013
www.ti.com
Application Information
A typical application circuit for the LMH0031 is shown in the Application Circuit diagram. This circuit
demonstrates the capabilities of the LMH0031 and allows its evaluation in a native configuration. An assembled
demonstration board is available, part number SD131EVK. The board may be ordered through any of TI's sales
offices. Complete circuit board layouts and schematics for the SD131EVK are available on TI's WEB site. For
latest availability information, please see: www.ti.com/appinfo/interface.
PCB LAYOUT AND POWER SYSTEM BYPASS RECOMMENDATIONS
Circuit board layout and stack-up for the LMH0031 should be designed to provide noise-free power to the device.
Good layout practice also will separate high frequency or high-level inputs and outputs from low-level inputs to
minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly
improved by using thin dielectrics (4 to 10 mils) for power/ground sandwiches. This increases the intrinsic
capacitance of the PCB power system which improves power supply filtering, especially at high frequencies, and
makes the value and placement of external bypass capacitors less critical. External bypass capacitors should
include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the range 0.01 µF to
0.1 µF. Tantalum capacitors may be in the range 2.2 µF to 10 µF. Voltage rating for tantalum capacitors should
be at least 5X the power supply voltage being used. It is recommended practice to use two vias at each power
pin of the LMH0031 as well as all RF bypass capacitor terminals. Dual vias reduce the interconnect inductance
by up to half, thereby extending the effective frequency range of the bypass components.
The outer layers of the PCB may be flooded with additional V_SS (ground) plane. These planes will improve
shielding and isolation as well as increase the intrinsic capacitance of the power supply plane system. Naturally,
to be effective, these planes must be tied to the V_SS power supply plane at frequent intervals with vias. Frequent
via placement also improves signal integrity on signal transmission lines by providing short paths for image
currents which reduces signal distortion. The planes should be pulled back from all transmission lines and
component mounting pads a distance equal to the width of the widest transmission line or the thickness of the
dielectric separating the transmission line from the internal power or ground plane(s) whichever is greater. Doing
so minimizes effects on transmission line impedances and reduces unwanted parasitic capacitances at
component mounting pads.
In especially noisy power supply environments, such as is often the case when using switching power supplies,
separate filtering may be used at the LMH0031's PLL and serial input power pins. The LMH0031 was designed
for this situation. The I/O, digital section, PLL and serial input power supply feeds are independent (see table and
Block Diagram for details). Supply filtering may take the form of L-section or pi-section, L-C filters in series with
these V_DD inputs. Such filters are available in a single package from several manufacturers. Device power
supplies must be either sequenced as described in POWER SUPPLIES, POWER-ON-RESET AND RESET
INPUT and ideally should be applied simultaneously as from a common source.
MAINTAINING OUTPUT DATA INTEGRITY
The way in which the TRS and other video data characters are specified and are therefore output in parallel form
can result in the simultaneous switching of many of the LMH0031’s CMOS outputs. Such switching can lead to
the production of output high level droop or low level ground bounce. Given in the specifications, V_OLP is the peak
output LOW voltage or ground bounce and V_OHV is the lowest output HIGH voltage or output droop that may
occur under dynamic simultaneous output switching conditions. V_OHV and V_OLP are measured with respect to
reference ground. Careful attention to PCB layout, power pin connections to the power planes and timing of the
output data clocking can reduce these effects. Consideration must also be given to the timing allocated to
external circuits which sample the outputs.
The effects of simultaneous output switching on output levels may be minimized by adopting good PCB layout
and data output timing practices, especially critical at HD data rates. The power pins feeding the I/O should have
low inductance connections to the power and ground planes. It is recommended that these connections use at
least two vias per power or ground pin. Short interconnecting traces consistent with good layout practices and
soldering rules must be used. Sampling or clocking of data by external devices should be so timed as to take
maximum advantage of the steady-state portion of the parallel output data interval. The LMH0031 is designed so
that video data will be stable at the positive-going transition of V_CLK. Data should not be sampled close to the
data transition intervals associated with the negative-going clock edge. The specified propagation delay and
clock to data timing parameters must be observed. When data is being sampled from the video data port
together with the ANC port and/or I/O port, it is recommended that the sampling clocks be synchronized with the
video clock, V_CLK, to minimize possible effects from ground bounce or output droop on sampled signal levels.
32
Submit Documentation Feedback
Product Folder Links: LMH0031
Copyright © 2006–2013, Texas Instruments Incorporated