LMH0031 Datasheet, PDF (34/39 Pages) National Semiconductor (TI) – SMPTE 292M/259M Digital Video Deserializer Descrambler with Video and Ancillary Data FIFOs

LMH0031
SNLS218A – JANUARY 2006 – REVISED APRIL 2013
LMC7101
+
-
100 k:
182 k:
+3.3V
V_{CTRL 74.25 MHz} F_OUT
VCXO
NC7SZ126
OE ^22.1:
+3.3V
V_{CTRL 27.00 MHz} F_OUT
VCXO
NC7SZ125
OE ^22.1:
CLC031 IO3 - SD/HD
CLC031 IO4 - Lock Detect
NC7SZ08
22.1 k:
100 pF
R_{B B}
V_CLK
LMH0031
R_REF DV[19:0]
To other
logic or
serializer
10 nF
4.75 k: ^{CAUTION! Read text}
before using this
circuit.
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Figure 8. Using Dual VCXOs for VCLK Example
The control voltage output from R_BB is externally filtered by the loop filter consisting of a 22.1kΩ resistor in series
with a 10nF capacitor, combined in parallel with a 100pF capacitor. This gives a loop bandwidth of 1.5kHz. Since
the control voltage is limited to around 2.1V, it requires a level shifter to get the entire pull range on the VCXO.
TI's LMC7101 is recommended with 100kΩ and 182kΩ resistors as shown in Figure 8 to provide a gain of 1.55,
sufficient to drive a 3.3V VCXO.
Recommended VCXOs from SaRonix (141 Jefferson Drive, Menlo Park, CA 94025, USA) include the
ST1308AAB-74.25 for high definition and the ST1307BAB-27.00 for standard definition. Dual VCXOs require
some supporting logic to select the appropriate VCXO. This requires the use of Format[4] (SD/HD) and Lock
Detect, which are mapped at power-on to I/O Port Bit 3 and I/O Port Bit 4, respectively. These two signals pass
through an AND gate (Fairchild Semiconductor's NC7SZ08 or similar). Its output is high when both Lock Detect
and Format[4] are high, which indicates a valid high-definition signal is present. The VCXOs are buffered to
control the transition times and to allow easy selection. The output of the AND gate is used to control the Output
Enable (OE) function of the buffers. The 74.25MHz VCXO is buffered with the NC7SZ126 with the AND gate
output connected to the OE pin of the NC7SZ126, and the 27.00MHz VCXO is buffered with the NC7SZ125 with
the AND gate output connected to the OE pin of the NC7SZ125. This circuit uses the 27.00MHz VCXO as
default and enables the 74.25MHz VCXO when a valid high-definition signal is present. The outputs from the
buffers are daisy-chained together and sent to the LMH0031's V_CLK in addition to other devices, such as the
LMH0030 serializer.
34
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