LMH0031 Datasheet, PDF (15/39 Pages) National Semiconductor (TI) – SMPTE 292M/259M Digital Video Deserializer Descrambler with Video and Ancillary Data FIFOs

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LMH0031
SNLS218A – JANUARY 2006 – REVISED APRIL 2013
Figure 4. Control Data Write Timing
Ancillary Data Functions
The LMH0031 can recover Ancillary Data from the serial data stream. This Ancillary Data and related control
characters are defined in the relevant SMPTE standards and may reside in the horizontal and vertical blanking
intervals. The data can consist of different types of message packets including audio data. The serial Ancillary
Data space must be formatted according to SMPTE 291M. The LMH0031 supports Ancillary Data in the
chrominance channel (C’r/C’b) only for high-definition operation. Ancillary Data for standard definition
follows the requirements of SMPTE 125M.
The Ancillary Data FIFO is sized to handle a maximum length ANC data Type 1 or Type 2 packet without the
ANC Flag, 259 words. Defined in SMPTE 291M, the packet consists of the Ancillary Data Flag, a 3-word Data ID
and Data Count, 255 8- or 10-bit User Data Words and a Checksum. The design of the LMH0031 Ancillary Data
FIFO also allows storage of up to 8 shorter length messages with total length not exceeding 259 words including
all ID information. Ancillary Data is copied from the data stream into the Ancillary Data FIFO. The parallel
Ancillary Data will still be present in the parallel chroma output DV[9:0]. ancillary flag information is not extracted
into the FIFO.
Copying of ANC data from the video data into the FIFO is controlled by the ANC Mask and ANC ID bits in the
control registers. A system of flags, ANC FIFO Empty, ANC FIFO 90% Full, ANC FIFO Full and ANC FIFO
Overrun are used to monitor FIFO status. The details and functions of these and other control words are
explained later in this datasheet.
Figure 5 shows the relationship of clock, data and control signals for reading Ancillary Data from the port
AD[9:0]. In Ancillary Data read mode, 10-bit Ancillary Data is routed from the Ancillary Data FIFO and read
from the port AD[9:0] at a rate determined by A_CLK.
Ancillary Data read (output) mode is invoked by making the ANC/CTRL input high and the RD/WR input high.
Ancillary Data is clocked from the FIFO on the L-H transition of A_CLK. Data may be read from the port on rising
edges of A_CLK, after the specified propagation delay, until the FIFO is emptied. Data may only be read from the
port when in the Ancillary Data mode. Ancillary Data cannot be written to the port.
To conserve power when the Ancillary Data function is not being used, the internal Ancillary Data FIFO clock is
disabled. This clock must be enabled before Ancillary Data may be replicated into the FIFO for output. This
internal FIFO clock is controlled by FIFO CLOCK ENABLE, bit-6 of the ANC 5 register (address 17h). The
default condition of FIFO CLOCK ENABLE is OFF. After enabling the internal FIFO clock by turning this bit ON,
A_CLK must be toggled three (3) times to propagate the enable to the clock tree.
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