LMH0031 Datasheet, PDF (23/39 Pages) National Semiconductor (TI) – SMPTE 292M/259M Digital Video Deserializer Descrambler with Video and Ancillary Data FIFOs

LMH0031
www.ti.com
SNLS218A – JANUARY 2006 – REVISED APRIL 2013
EDH 2 (register 03h)
The EDH Ancillary Data flags ANC UES, ANC IDA, ANC IDH, ANC EDA andANC EDH are defined in SMPTE
RP 165. The flags are updated automatically when the EDH function is enabled and data is being received.
The status of EDH flag errors in incoming SD serial data are reported in the ffFlagError, apFlagError and
ancFlagError bits. Each of these bits is the logical-OR of the corresponding EDH and EDA flags.
ANC 0 (Address 04h)
The V FIFO Depth[2:0] bits control the depth of the video FIFO which preceeds the parallel output data drivers.
The depth can be set from 0 to 4 stages by writing the corresponding binary code into these bits. For example: to
set the Video FIFO depth at two registers, load 11010XXXXXb into the ANC 0 control register (where X
represents the other functional bits of this register).
NOTE
When changing some but not all bits in a register and to retain unchanged other data
previously stored in the register, read the register’s contents and logically-OR this with the
new data. Then write the modified data back into the register.
Flags for ANC FIFO EMPTY, ANC FIFO 90% FULL, ANC FIFO FULL and ANC FIFO OVERRUN are available
in the configuration and control register set. These flags can also be assigned as outputs on the multi-function
I/O port. ANC FIFO EMPTY when set indicates that the FIFO contains no data. ANC FIFO 90% FULL indicates
when the FIFO is at 90% of capacity. Since it is virtually impossible for the host processor to begin extracting
data from the FIFO after it has been flagged as full without the possibility of an overrun condition occurring, ANC
FIFO 90% FULL is used as an advanced command to the host to begin extracting data from the FIFO. To be
used properly, ANC FIFO 90% FULL should be assigned as an output on the multi-function I/O port and
monitored by the host system. Otherwise, inadvertent loss of ancillary packet data could occur. ANC FIFO FULL
when set indicates that the FIFO registers are completely filled with data.
The ANC FIFO OVERRUN flag indicates that an attempt to write data into a full FIFO has occurred. ANC FIFO
OVERRUN can be reset by reading the bit's status via the ancillary/Control port. If an overrun occurrs, the status
of the FIFO message tracking will be invalidated. In this event, the FIFO should be flushed to reset the message
tracking pointers. Any messages then in the FIFO will be lost.
The ANC Checksum Force bit, under certain conditions, enables the overwriting of Ancillary Data checksums
received in the data. Calculation and insertion of new Ancillary Data checksums is controlled by the ANC
Checksum Force bit. If a checksum error is detected (calculated and received checksums do not match) and the
ANC Checksum Force bit is set, the ANC Checksum Error bit is set and a new checksum is inserted in the
Ancillary Data replacing the previous one. If a checksum error is detected and the ANC Checksum Force bit is
not set, the checksum mismatch is reported via the ANC Checksum Error bit. ANC Checksum Error is
available as an output on the multifunction I/O port.
ANC 1 AND 2 (Addresses 05h and 06h)
The extraction of Ancillary Data packets from video data into the FIFO is controlled by the ANC MASK[15:0] and
ANC ID[15:0] bits in the control registers. The ANC ID[7:0] register normally is set to a valid 8-bit code used for
component Ancillary Data packet DID identification as specified in SMPTE 291M-1998. Similarly, ANC ID[15:8]
normally is set to a valid 8-bit code used for component Ancillary Data packet SDID/DBN identification.
ANC 3 AND 4 (Addresses 07h and 08h)
The ANC MASK[7:0] is an 8-bit word that can be used to selectively control extraction of packets with specific
DIDs (or DID ranges) into the FIFO. When the ANC MASK[7:0] is set to FFh, packets with any DID can be
extracted into the FIFO. When any bit or bits of the ANC MASK[7:0] are set to a logic-1, the corresponding bit or
bits of the ANC ID[7:0] are a don't-care when matching DIDs of packets being extracted. When the ANC
MASK[7:0] is set to 00h, the ANC DID of incoming packets must match exactly, bit-for-bit the ANC ID[7:0] set in
the control register for the packets to be extracted into the FIFO. The initial value of the ANC MASK[7:0] is FFh
and the ANC ID[7:0] is 00h.
Similarly, ANC MASK[15:8] is an 8-bit word that can be used to selectively control extraction of packets with
specific SDID/DBN (or SDID/DBN ranges) into the FIFO. Operation and use of these bits is the same as for ANC
MASK[7:0] previously discussed.
Copyright © 2006–2013, Texas Instruments Incorporated
Submit Documentation Feedback
23
Product Folder Links: LMH0031