LMH0031 Datasheet, PDF (17/39 Pages) National Semiconductor (TI) – SMPTE 292M/259M Digital Video Deserializer Descrambler with Video and Ancillary Data FIFOs

LMH0031
www.ti.com
SNLS218A – JANUARY 2006 – REVISED APRIL 2013
EDH/CRC SYSTEM
The LMH0031 has EDH and CRC character generation and checking circuitry. The EDH system functions as
described in SMPTE Recommended Practice RP-165. The CRC system functions as specified in SMPTE 292M.
The EDH/CRC polynomial generators/checkers accept parallel data from the de-serializing system and
generate the EDH and CRC check words for comparison with those received in the data.
The EDH Enable bit in the control register enables the EDH generation and checking system. Incoming SDTV
data is checked for errors and the EDH flags are updated automatically. EDH errors are reported in the EDH0,
EDH1, and EDH2 register sets of the configuration and control registers.
Updated or new EDH check words and flags may be generated and inserted in the data. EDH check words are
generated using the polynomial X¹⁶ + X¹² + X⁶ + 1 per SMPTE RP165. Generation and automatic insertion of
new or corrected EDH check words is controlled by EDH Force and EDH Enable bits in the control registers.
EDH check words and status flags are inserted in the parallel data at the correct positions in the Ancillary Data
space and formatted per SMPTE 291M. After a reset, the initial state of all EDH and CRC check characters is
00h.
The SMPTE 292M high definition video standard employs CRC (cyclic redundancy check codes) error checking
instead of EDH. The CRC consists of two 18-bit words generated using the polynomial X¹⁸ + X⁵ + X⁴ + 1 per
SMPTE 292M. One CRC is used for luminance and one for chrominance data. The CRCs appear in the data
stream following the EAV and line number characters. The CRCs are checked and errors are reported in the
EDH0, EDH1, and EDH2 register sets of the configuration and control registers.
PHASE-LOCKED LOOP / CLOCK-DATA RECOVERY SYSTEM
The phase-locked loop and clock-data recovery (PLL/CDR) system generates all internal timing and data rate
clocks for the LMH0031. The PLL/CDR system consists of five main functional blocks: 1) the input buffer which
receives the incoming data, 2) input data samplers which oversample the data coming from the input buffer, 3) a
PLL (VCO, divider chain, phase-frequency detector and internal loop filter) which generates sampling and other
system clocks, 4) a digital CDR system to recover the oversampled serial input data from the samplers and the
digital system control and 5) a rate detect controller which sequences the PLL to find the data rate.
Using an oversampling technique, the timing information encoded in the serial data is extracted and used to
synchronize the recovered clock and data. The parallel data rate and other clock signals are derived from the
regenerated serial clock. The parallel data rate clock is 1/10th of the serial data rate clock for standard definition
or 1/20th of the serial data clock frequency for high definition. The data interface between the CDR and the
digital processing block uses 10-bit data plus the required clocks.
The PLL is held in coarse frequency lock by an external 27MHz clock signal, EXT CLK, or by an external 27MHz
crystal and internal oscillator. Upon power-on, EXT CLK is the default reference. The internal oscillator and an
external crystal may be used as the reference by setting the OSCEN bit in the CDR register. The reference
clock reduces lock latency and enhances format and auto-rate detection robustness. PLL acquisition, data phase
alignment and format detection time is 20ms or less at 1.485Mbps. The VCO has separate V_DDPLL and V_SSPLL
power supply feeds, pins 51 and 52, which may be supplied power via an external low-pass filter, if desired.
pin 60
pin 61
33pF
27MHz
33pF
Figure 7. Crystal and Load Circuit
A 27MHz crystal and load circuit may be used to provide the reference clock. A fundamental mode crystal with
the following parameters is used: frequency 27MHz, frequency tolerance ±30ppm, load capacitance 18pF,
maximum drive level 100µW, equivalent series resistance <50Ω, operating temperature range 0°C to 70°C. Refer
to Figure 7 for a typical load circuit and connection information.
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