LM3S2276 Datasheet, PDF (706/785 Pages) Texas Instruments – Stellaris® LM3S2276 Microcontroller

Pulse Width Modulator (PWM)
Register 74: PWM0 Fault Status 0 (PWM0FLTSTAT0), offset 0x804
Register 75: PWM1 Fault Status 0 (PWM1FLTSTAT0), offset 0x884
Register 76: PWM2 Fault Status 0 (PWM2FLTSTAT0), offset 0x904
Register 77: PWM3 Fault Status 0 (PWM3FLTSTAT0), offset 0x984
Along with the PWMnFLTSTAT1 register, this register provides status regarding the fault condition
inputs.
If the LATCH bit in the PWMnCTL register is clear, the contents of the PWMnFLTSTAT0 register
are read-only (RO) and provide the current state of the FAULTn inputs.
If the LATCH bit in the PWMnCTL register is set, the contents of the PWMnFLTSTAT0 register are
read / write 1 to clear (R/W1C) and provide a latched version of the FAULTn inputs. In this mode,
the register bits are cleared by writing a 1 to a set bit. The FAULTn inputs are recorded after their
sense is adjusted in the generator.
The contents of this register can only be written if the fault source extensions are enabled (the
FLTSRC bit in the PWMnCTL register is set).
PWM0 Fault Status 0 (PWM0FLTSTAT0)
Base 0x4002.8000
Offset 0x804
Type -, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
FAULT2 FAULT1 FAULT0
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
-
-
-
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:3
2
1
Name
reserved
FAULT2
FAULT1
Type
RO
-
-
Reset
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Fault Input 2
The same function as FAULT0, except applied for the FAULT2 input.
Fault Input 1
The same function as FAULT0, except applied for the FAULT1 input.
706
November 17, 2011
Texas Instruments-Production Data