LM3S2276 Datasheet, PDF (132/785 Pages) Texas Instruments – Stellaris® LM3S2276 Microcontroller

Cortex-M3 Peripherals
Bit/Field
4
3
2
1
0
Name
DIV0
UNALIGNED
reserved
MAINPEND
BASETHR
Type
R/W
R/W
RO
R/W
R/W
Reset
0
Description
Trap on Divide by 0
This bit enables faulting or halting when the processor executes an
SDIV or UDIV instruction with a divisor of 0.
Value Description
0 Do not trap on divide by 0. A divide by zero returns a quotient
of 0.
1 Trap on divide by 0.
0
Trap on Unaligned Access
Value Description
0 Do not trap on unaligned halfword and word accesses.
1 Trap on unaligned halfword and word accesses. An unaligned
access generates a usage fault.
Unaligned LDM, STM, LDRD, and STRD instructions always fault
regardless of whether UNALIGNED is set.
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
Allow Main Interrupt Trigger
Value Description
0 Disables unprivileged software access to the SWTRIG register.
1 Enables unprivileged software access to the SWTRIG register
(see page 121).
0
Thread State Control
Value Description
0 The processor can enter Thread mode only when no exception
is active.
1 The processor can enter Thread mode from any level under the
control of an EXC_RETURN value (see “Exception
Return” on page 87 for more information).
132
November 17, 2011
Texas Instruments-Production Data