LM3S2276 Datasheet, PDF (624/785 Pages) Texas Instruments – Stellaris® LM3S2276 Microcontroller

Controller Area Network (CAN) Module
[Sync + Prop + Phase1 + Phase2] × t_q
The data in the CANBIT register is the configuration input of the CAN protocol controller. The baud
rate prescaler (configured by the BRP field) defines the length of the time quantum, the basic time
unit of the bit time; the bit timing logic (configured by TSEG1, TSEG2, and SJW) defines the number
of time quanta in the bit time.
The processing of the bit time, the calculation of the position of the sample point, and occasional
synchronizations are controlled by the CAN controller and are evaluated once per time quantum.
The CAN controller translates messages to and from frames. In addition, the controller generates
and discards the enclosing fixed format bits, inserts and extracts stuff bits, calculates and checks
the CRC code, performs the error management, and decides which type of synchronization is to be
used. The bit value is received or transmitted at the sample point. The information processing time
(IPT) is the time after the sample point needed to calculate the next bit to be transmitted on the CAN
bus. The IPT includes any of the following: retrieving the next data bit, handling a CRC bit, determining
if bit stuffing is required, generating an error flag or simply going idle.
The IPT is application-specific but may not be longer than 2 t_q; the CAN's IPT is 0 t_q. Its length is
the lower limit of the programmed length of Phase2. In case of synchronization, Phase2 may be
shortened to a value less than IPT, which does not affect bus timing.
16.3.16
Calculating the Bit Timing Parameters
Usually, the calculation of the bit timing configuration starts with a required bit rate or bit time. The
resulting bit time (1/bit rate) must be an integer multiple of the system clock period.
The bit time may consist of 4 to 25 time quanta. Several combinations may lead to the required bit
time, allowing iterations of the following steps.
The first part of the bit time to be defined is Prop. Its length depends on the delay times measured
in the system. A maximum bus length as well as a maximum node delay has to be defined for
expandable CAN bus systems. The resulting time for Prop is converted into time quanta (rounded
up to the nearest integer multiple of t_q).
Sync is 1 t_q long (fixed), which leaves (bit time - Prop - 1) t_q for the two Phase Buffer Segments. If
the number of remaining t_q is even, the Phase Buffer Segments have the same length, that is,
Phase2 = Phase1, else Phase2 = Phase1 + 1.
The minimum nominal length of Phase2 has to be regarded as well. Phase2 may not be shorter
than the CAN controller's Information Processing Time, which is, depending on the actual
implementation, in the range of [0..2] t_q.
The length of the synchronization jump width is set to the least of 4, Phase1 or Phase2.
The oscillator tolerance range necessary for the resulting configuration is calculated by the formula
given below:
(1 − df ) × fnom ≤ fosc ≤ (1 + df ) × fnom
wh_de_fre: _≤
(Phase _ seg1,Phase _ seg2) min
2 × (13 × tbit − Phase _ Seg2)
■ df = Maximum tolerance of oscillator frequency
■ fos_dc_f=_mA_ac_xtua₌l os₂cil_×lat_dor_ffre_×qu_fe_nn_ocy_m
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November 17, 2011
Texas Instruments-Production Data