LM3S2276 Datasheet, PDF (641/785 Pages) Texas Instruments – Stellaris® LM3S2276 Microcontroller

Stellaris® LM3S2276 Microcontroller
Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024
Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084
Reading the Command Mask registers provides status for various functions. Writing to the Command
Mask registers specifies the transfer direction and selects which buffer registers are the source or
target of the data transfer.
Note that when a read from the message object buffer occurs when the WRNRD bit is clear and the
CLRINTPND and/or NEWDAT bits are set, the interrupt pending and/or new data flags in the message
object buffer are cleared.
CAN IF1 Command Mask (CANIF1CMSK)
CAN0 base: 0x4004.0000
Offset 0x024
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
WRNRD MASK
ARB CONTROL CLRINTPND ^{NEWDAT /} DATAA DATAB
TXRQST
Type RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:8
7
6
5
4
Name
reserved
WRNRD
MASK
ARB
CONTROL
Type
RO
R/W
R/W
R/W
R/W
Reset Description
0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
Write, Not Read
Transfer the message object address specified by the CAN Command
Request (CANIFnCRQ) register to the CAN message buffer registers.
Note:
Interrupt pending and new data conditions in the message
buffer can be cleared by reading from the buffer (WRNRD = 0)
when the CLRINTPND and/or NEWDAT bits are set.
0
Access Mask Bits
0: Mask bits unchanged.
1: Transfer IDMASK + DIR + MXTD of the message object into the
Interface registers.
0
Access Arbitration Bits
0: Arbitration bits unchanged.
1: Transfer ID + DIR + XTD + MSGVAL of the message object into the
Interface registers.
0
Access Control Bits
0: Control bits unchanged.
1: Transfer control bits from the CANIFnMCTL register into the Interface
registers.
November 17, 2011
641
Texas Instruments-Production Data