LM3S2276 Datasheet, PDF (11/785 Pages) Texas Instruments – Stellaris® LM3S2276 Microcontroller

Stellaris® LM3S2276 Microcontroller
Figure 14-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 536
Figure 14-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 537
Figure 14-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 537
Figure 14-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 538
Figure 14-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 539
Figure 14-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 539
Figure 14-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 540
Figure 14-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 541
Figure 14-10. MICROWIRE Frame Format (Single Frame) ........................................................ 541
Figure 14-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 542
Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 543
Figure 15-1. I²C Block Diagram ............................................................................................. 573
Figure 15-2. I²C Bus Configuration ........................................................................................ 574
Figure 15-3. START and STOP Conditions ............................................................................. 574
Figure 15-4. Complete Data Transfer with a 7-Bit Address ....................................................... 575
Figure 15-5. R/S Bit in First Byte ............................................................................................ 575
Figure 15-6. Data Validity During Bit Transfer on the I²C Bus ................................................... 575
Figure 15-7. Master Single SEND .......................................................................................... 579
Figure 15-8. Master Single RECEIVE ..................................................................................... 580
Figure 15-9. Master Burst SEND ........................................................................................... 581
Figure 15-10. Master Burst RECEIVE ...................................................................................... 582
Figure 15-11. Master Burst RECEIVE after Burst SEND ............................................................ 583
Figure 15-12. Master Burst SEND after Burst RECEIVE ............................................................ 584
Figure 15-13. Slave Command Sequence ................................................................................ 585
Figure 16-1. CAN Controller Block Diagram ............................................................................ 610
Figure 16-2. CAN Data/Remote Frame .................................................................................. 611
Figure 16-3. Message Objects in a FIFO Buffer ...................................................................... 619
Figure 16-4. CAN Bit Time .................................................................................................... 623
Figure 17-1. PWM Unit Diagram ............................................................................................ 656
Figure 17-2. PWM Module Block Diagram .............................................................................. 657
Figure 17-3. PWM Count-Down Mode .................................................................................... 658
Figure 17-4. PWM Count-Up/Down Mode .............................................................................. 659
Figure 17-5. PWM Generation Example In Count-Up/Down Mode ........................................... 659
Figure 17-6. PWM Dead-Band Generator ............................................................................... 660
Figure 18-1. 64-Pin LQFP Package Pin Diagram .................................................................... 708
Figure 21-1. Load Conditions ................................................................................................ 723
Figure 21-2. JTAG Test Clock Input Timing ............................................................................. 726
Figure 21-3. JTAG Test Access Port (TAP) Timing .................................................................. 726
Figure 21-4. External Reset Timing (RST) .............................................................................. 727
Figure 21-5. Power-On Reset Timing ..................................................................................... 727
Figure 21-6. Brown-Out Reset Timing .................................................................................... 728
Figure 21-7. Software Reset Timing ....................................................................................... 728
Figure 21-8. Watchdog Reset Timing ..................................................................................... 728
Figure 21-9. Hibernation Module Timing ................................................................................. 729
Figure 21-10. ADC Input Equivalency Diagram ......................................................................... 730
Figure 21-11. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................... 731
Figure 21-12. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 732
November 17, 2011
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