LM3S2276 Datasheet, PDF (586/785 Pages) Texas Instruments – Stellaris® LM3S2276 Microcontroller

Inter-Integrated Circuit (I²C) Interface
TPR = (System Clock / (2 * (SCL_LP + SCL_HP) * SCL_CLK)) - 1;
TPR = (20MHz / (2 * (6 + 4) * 100000)) - 1;
TPR = 9
Write the I2CMTPR register with the value of 0x0000.0009.
6. Specify the slave address of the master and that the next operation will be a Send by writing
the I2CMSA register with a value of 0x0000.0076. This sets the slave address to 0x3B.
7. Place data (byte) to be sent in the data register by writing the I2CMDR register with the desired
data.
8. Initiate a single byte send of the data from Master to Slave by writing the I2CMCS register with
a value of 0x0000.0007 (STOP, START, RUN).
9. Wait until the transmission completes by polling the I2CMCS register’s BUSBSY bit until it has
been cleared.
15.5
Register Map
Table 15-3 on page 586 lists the I²C registers. All addresses given are relative to the I²C base
addresses for the master and slave:
■ I²C 0: 0x4002.0000
Note that the I²C module clock must be enabled before the registers can be programmed (see
page 221). There must be a delay of 3 system clocks after the I²C module clock is enabled before
any I²C module registers are accessed.
The hw_i2c.h file in the StellarisWare^® Driver Library uses a base address of 0x800 for the I²C slave
registers. Be aware when using registers with offsets between 0x800 and 0x818 that StellarisWare
uses an offset between 0x000 and 0x018 with the slave base address.
Table 15-3. Inter-Integrated Circuit (I²C) Interface Register Map
Offset Name
I²C Master
0x000 I2CMSA
0x004 I2CMCS
0x008 I2CMDR
0x00C I2CMTPR
0x010 I2CMIMR
0x014 I2CMRIS
0x018 I2CMMIS
0x01C I2CMICR
0x020 I2CMCR
Type
Reset
Description
R/W
0x0000.0000 I2C Master Slave Address
R/W
0x0000.0000 I2C Master Control/Status
R/W
0x0000.0000 I2C Master Data
R/W
0x0000.0001 I2C Master Timer Period
R/W
0x0000.0000 I2C Master Interrupt Mask
RO
0x0000.0000 I2C Master Raw Interrupt Status
RO
0x0000.0000 I2C Master Masked Interrupt Status
WO
0x0000.0000 I2C Master Interrupt Clear
R/W
0x0000.0000 I2C Master Configuration
See
page
588
589
593
594
595
596
597
598
599
586
November 17, 2011
Texas Instruments-Production Data