DS90UH949-Q1 Datasheet, PDF (66/87 Pages) Texas Instruments – 1080p HDMI to FPD-Link III Bridge Serializer with HDCP

DS90UH949-Q1
SNLS453 – NOVEMBER 2014
www.ti.com
Register Maps (continued)
ADD
(dec)
194
ADD
(hex)
0xC2
Register Name
HDCP_CFG
Bit(s)
7
6
5
4:3
2
1
0
Table 10. Serial Control Bus Registers (continued)
Register
Type
RW
RW
RW
RW
RW
RW
RW
Default
(hex)
0xA8
Function
Description
ENH_LV
HDCP_EESS
TX_RPTR
ENC_MODE
WAIT_100MS
RX_DET_SEL
HDCP_AVMU
TE
Enable Enhanced Link Verification: Enables enhanced link verification. Allows checking
of the encryption Pj value on every 16th frame.
0 = Enhanced Link Verification disabled.
1 = Enhanced Link Verification enabled.
Enable Enhanced Encryption Status Signaling: Enables Enhanced Encryption Status
Signaling (EESS) instead of the Original Encryption Status Signaling (OESS).
0 = OESS mode enabled.
1 = EESS mode enabled.
Transmit Repeater Enable: Enables the transmitter to act as a repeater. In this mode, the
HDCP Transmitter incorporates the additional authentication steps required of an HDCP
Repeater.
0 = Transmit Repeater mode disabled.
1 = Transmit Repeater mode enabled.
Encryption Control Mode: Determines mode for controlling whether encryption is required
for video frames.
00 = Enc_Authenticated.
01 = Enc_Reg_Control.
10 = Enc_Always.
11 = Enc_InBand_Control (per frame).
Enable 100MS Wait: The HDCP 1.3 specification allows for a 100Ms wait to allow the
HDCP Receiver to compute the initial encryption values. The FPD-LinkIII implementation
guarantees that the Receiver will complete the computations before the HDCP
Transmitter. Thus the timer is unnecessary. To enable the 100ms timer, set this bit to a 1.
RX Detect Select: Controls assertion of the Receiver Detect Interrupt. If set to 0, the
Receiver Detect Interrupt will be asserted on detection of an FPD-Link III Receiver. If set
to 1, the Receiver Detect Interrupt will also require a receive lock indication from the
receiver.
Enable AVMUTE: Setting this bit to a 1 will initiate AVMUTE operation. The transmitter
will ignore encryption status controls while in this state. If this bit is set to a 0, normal
opera¬tion will resume. This bit may only be set if the HDCP_EESS bit is also set.
66
Submit Documentation Feedback
Product Folder Links: DS90UH949-Q1
Copyright © 2014, Texas Instruments Incorporated