DS90UH949-Q1 Datasheet, PDF (11/87 Pages) Texas Instruments – 1080p HDMI to FPD-Link III Bridge Serializer with HDCP

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7.6 AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
GPIO FREQUENCY⁽¹⁾
TEST CONDITIONS
PIN/FREQ.
MIN
R_b,FC
Forward Channel GPIO Single-Lane, IN_CLK = 25MHz GPIO[3:0],
Frequency
- 96MHz
D_GPIO[3:0]
Dual-Lane, IN_CLK/2 = 25MHz
- 85MHz
t_GPIO,FC
GPIO Pulse Width,
Forward Channel
Single-Lane, IN_CLK = 25MHz
- 96MHz
GPIO[3:0],
D_GPIO[3:0]
>2 / IN_CLK
Dual-Lane, IN_CLK/2 = 25MHz
- 85MHz
>2 /
(IN_CLK/2)
TMDS INPUT
Skew-Intra Maximum Intra-Pair
Skew
IN_CLK±,
IN_D[2:0]±
Skew-Inter Maximum Inter-Pair
Skew
I_TJIT
Input Total Jitter
Tolerance
IN_CLK±
0.3
FPD-LINK III OUTPUT
t_LHT
Low Voltage Differential
Low-to-High Transition
Time
t_HLT
Low Voltage Differential
High-to-Low Transition
Time
t_XZD
Output Active to OFF
Delay
PDB = L
t_PLD
Lock Time (HDMI Rx)
t_SD
Delay — Latency
Random Pattern
t_DJIT
Output Total
Jitter(Figure 5 )
IN_CLK±
Single-Lane:
High pass
filter
IN_CLK/20
Dual-lane:
High pass
filter
IN_CLK/40
λ_STXBW
Jitter Transfer Function
(-3dB Bandwidth)
δ_STX
Jitter Transfer Function
Peaking
(1) Back channel rates are available on the companion deserializer datasheet.
(2) One bit period of the TMDS input.
(3) Ten bit periods of the TMDS input.
(4) One bit period of the serializer output.
DS90UH949-Q1
SNLS453 – NOVEMBER 2014
TYP
MAX
UNIT
0.25 *
IN_CLK
0.125 *
IN_CLK
MHz
s
0.4 UI_TMDS ⁽²⁾
0.2*T_char ⁽³⁾
ns
+ 1.78ns
UI_TMDS ⁽²⁾
80
ps
80
ps
100
ns
5
ms
145*T ⁽²⁾
s
0.3
UI_FPD3 ⁽⁴⁾
960
kHz
0.1
dB
Copyright © 2014, Texas Instruments Incorporated
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