DS90UH949-Q1 Datasheet, PDF (5/87 Pages) Texas Instruments – 1080p HDMI to FPD-Link III Bridge Serializer with HDCP

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DS90UH949-Q1
SNLS453 – NOVEMBER 2014
Pin Functions (continued)
NAME
PIN
NO.
I/O, TYPE
DESCRIPTION
BIDIRECTIONAL CONTROL CHANNEL (BCC) GPIO PINS
GPIO0
4
IO, LVCMOS BCC GPIO0. Shared with SDIN
GPIO1
5
IO, LVCMOS BCC GPIO1. Shared with SWC
GPIO2
37
IO, LVCMOS BCC GPIO2. Shared with I2S_DC
GPIO3
38
IO, LVCMOS BCC GPIO3. Shared with I2S_DD
REGISTER-ONLY GPIO
GPIO5_REG
36
IO, LVCMOS General Purpose Input/Output 5
Local register control only. Shared with I2S_DB
GPIO6_REG
35
IO, LVCMOS General Purpose Input/Output 6
Local register control only. Shared with I2S_DA
GPIO7_REG
33
IO, LVCMOS General Purpose Input/Output 7
Local register control only. Shared with I2S_WC
GPIO8_REG
34
IO, LVCMOS General Purpose Input/Output 8
Local register control only. Shared with I2S_CLK
SLAVE MODE LOCAL I2S CHANNEL PINS
I2S_WC
33
I, LVCMOS Slave Mode I2S Word Clock Input. Shared with GPIO7_REG
I2S_CLK
34
I, LVCMOS Slave Mode I2S Clock Input. Shared with GPIO8_REG
I2S_DA
35
I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO6_REG
I2S_DB
36
I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO5_REG
I2S_DC
37
I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO2
I2S_DD
38
I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO3
AUXILIARY I2S CHANNEL PINS
SWC
5
O, LVCMOS Master Mode I2S Word Clock Ouput. Shared with GPIO1
SCLK
6
O, LVCMOS Master Mode I2S Clock Ouput. Shared with I2CSEL. This pin is sampled following power-up
as I2CSEL, then it will switch to SCLK operation as an output.
SDIN
4
I, LVCMOS Master Mode I2S Data Input. Shared with GPIO0
MCLK
16
IO, LVCMOS Master Mode I2S System Clock Input/Output
POWER and GROUND
VTERM
57
Power 3.3V (±5%) Supply for DC-coupled internal termination OR
1.8V (±5%) Supply for AC-coupled internal termination
Refer to Figure 25 or Figure 26.
VDD18
24
Power 1.8 (±5%) Analog supply. Refer to Figure 25 or Figure 26.
51
64
VDDA11
9
Power 1.1V(±5%) Analog supply. Refer to Figure 25 or Figure 26.
VDDHA11
52
Power 1.1V(±5%) TMDS supply. Refer to Figure 25 or Figure 26.
54
58
61
VDDHS11
21
Power 1.1V(±5%) supply. Refer to Figure 25 or Figure 26.
28
VDDL11
7
Power 1.1V(±5%) Digital supply. Refer to Figure 25 or Figure 26.
41
VDDP11
17
Power 1.1V(±5%) PLL supply. Refer to Figure 25 or Figure 26.
VDDS11
25
Power 1.1V(±5%) Serializer supply. Refer to Figure 25 or Figure 26.
VDDIO
3
Power 1.8V (±5%) IO supply. Refer to Figure 25 or Figure 26.
46
GND
Thermal
Pad
GND
Ground. Connect to Ground plane with at least 9 vias.
OTHER
RES0
2
RES1
29
Reserved. Tie to GND.
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