DS90UH949-Q1 Datasheet, PDF (20/87 Pages) Texas Instruments – 1080p HDMI to FPD-Link III Bridge Serializer with HDCP

DS90UH949-Q1
SNLS453 – NOVEMBER 2014
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Feature Description (continued)
The device supports TMDS clocks in the range of 25 MHz to 96 MHz over one lane, or 50MHz to 170MHz over
two lanes. The FPD-Link III serial stream rate is 3.36 Gbps maximum (875 Mbps minimum) , or 2.975 Gbps
maximum per lane (875 Mbps minimum) when transmitting over both lanes.
8.3.9 Back Channel Data Transfer
The Backward Channel provides bidirectional communication between the display and host processor. The
information is carried from the deserializer to the serializer as serial frames. The back channel control data is
transferred over both serial links along with the high-speed forward data, DC balance coding and embedded
clock information. This architecture provides a backward path across the serial link together with a high speed
forward channel. The back channel contains the I2C, HDCP, CRC and 4 bits of standard GPIO information with
5, 10, or 20 Mbps line rate (configured by the compatible deserializer).
8.3.10 FPD-Link III Port Register Access
Since the DS90UH949-Q1 contains two downstream ports, some registers need to be duplicated to allow control
and monitoring of the two ports. To facilitate this, a TX_PORT_SEL register controls access to the two sets of
registers. Registers that are shared between ports (not duplicated) will be available independent of the settings in
the TX_PORT_SEL register.
Setting the TX_PORT0_SEL or TX_PORT1_SEL bit will allow a read of the register for the selected port. If both
bits are set, port1 registers will be returned. Writes will occur to ports for which the select bit is set, allowing
simultaneous writes to both ports if both select bits are set.
Setting the PORT1_I2C_EN bit will enable a second I2C slave address, allowing access to the second port
registers through the second I2C address. If this bit is set, the TX_PORT0_SEL and TX_PORT1_SEL bits will be
ignored.
8.3.11 Power Down (PDB)
The Serializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin may be controlled by an
external device, or through V_DDIO, where V_DDIO = 1.71V to 1.89V. To save power, disable the link when the
display is not needed (PDB = LOW). Ensure that this pin is not driven HIGH before all power supplies have
reached final levels. When PDB is driven low, ensure that the pin is driven to 0V for at least 3ms before releasing
or driving high. In the case where PDB is pulled up to V_DDIO directly, a 10kΩ pull-up resistor and a >10µF
capacitor to ground are required (See Power Up Requirements And PDB Pin).
Toggling PDB low will POWER DOWN the device and RESET all control registers to default. During this time,
PDB must be held low for a minimum of 3ms before going high again.
8.3.12 Serial Link Fault Detect
The DS90UH949-Q1 can detect fault conditions in the FPD-Link III interconnect. If a fault condition occurs, the
Link Detect Status is 0 (cable is not detected) on bit 0 of address 0x0C (Table 10). The DS90UH949-Q1 will
detect any of the following conditions:
1. Cable open
2. “+” to “-” short
3. ”+” to GND short
4. ”-” to GND short
5. ”+” to battery short
6. ”-” to battery short
7. Cable is linked incorrectly (DOUT+/DOUT- connections reversed)
Note: The device will detect any of the above conditions, but does not report specifically which one has occurred.
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