DS90UH949-Q1 Datasheet, PDF (54/87 Pages) Texas Instruments – 1080p HDMI to FPD-Link III Bridge Serializer with HDCP

DS90UH949-Q1
SNLS453 – NOVEMBER 2014
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Register Maps (continued)
ADD
(dec)
80
ADD
(hex)
0x50
Register Name
BRIDGE_STS
81
0x51 EDID_ID
82
0x52 EDID_CFG0
83
0x53 EDID_CFG1
Bit(s)
7
6
5
4
3
2
1
0
7:1
0
7
6:4
3:0
7:2
1:0
Table 10. Serial Control Bus Registers (continued)
Register
Type
R
R
R
R
R
R
R
R
RW
RW
RW
RW
RW
Default
(hex)
0x03
0x50
0
0x01
0x0E
0x00
Function
Description
RX5V_DETEC RX +5V detect: Indicates status of the RX_5V pin. When asserted, indicates the HDMI
T
interface has detected valid voltage on the RX_5V input.
HDMI_INT
HDMI Interrupt Status: Indicates an HDMI Interrupt is pending. HDMI interrupts are
serviced through the HDMI Registers via the APB Interface.
HDCP_INT
HDCP Interrupt Status: Indicates an HDCP Transmitter Interrupt is pending. HDCP
Transmit interrupts are serviced through the HDCP Interrupt Control and Status registers.
INIT_DONE
Initialization Done: Initialization sequence has completed. This step will complete after
configuration complete (CFG_DONE).
REM_EDID_L Remote EDID Loaded: Indicates EDID SRAM has been loaded from a remote EDID
OAD
EEPROM device over the Bidirectional Control Channel. The EDID_CKSUM value
indicates if the EDID load was successful.
CFG_DONE
Configuration Complete: Indicates automatic configuration has completed. This step will
complete prior to initialization complete (INIT_DONE).
CFG_CKSUM Configuration checksum status: Indicates result of Configuration checksum during
initialization. The device verifies the 2’s complement checksum in the last 128 bytes of
the EEPROM. A value of 1 indicates the checksum passed.
EDID_CKSUM EDID checksum Status: Indicates result of EDID checksum during EDID initialization. The
device verifies the 2’s complement checksum in the first 256 bytes of the EEPROM. A
value of 1 indicates the checksum passed.
EDID_ID
EDID I2C Slave Address: I2C address used for accessing the EDID information. These
are the upper 7 bits in 8-bit format addressing, where the lowest bit is the Read/Write
control.
EDID_RDONL EDID Read Only: Set to a 1 puts the EDID SRAM memory in read-only mode for access
Y
via the HDMI DDC interface. Setting to a 0 allows writes to the EDID SRAM memory.
Reserved.
EDID_SDA_H
OLD
Internal SDA Hold Time: This field configures the amount of internal hold time provided
for the DDC_SDA input relative to the DDC_SCL input. Units are 40 nanoseconds. The
hold time is used to qualify the start detection to avoid false detection of Start or Stop
conditions.
EDID_FLTR_D I2C Glitch Filter Depth: This field configures the maximum width of glitch pulses on the
PTH
DDC_SCL and DDC_SDA inputs that will be rejected. Units are 5 nanoseconds.
Reserved.
EDID_SDA_DL SDA Output Delay: This field configures output delay on the DDC_SDA output when the
Y
EDID memory is accessed. Setting this value will increase output delay in units of 40ns.
Nominal output delay values for DDC_SCL to DDC_SDA are:
00 : 240ns.
01 : 280ns.
10 : 320ns.
11 : 360ns.
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