DS90UH949-Q1 Datasheet, PDF (65/87 Pages) Texas Instruments – 1080p HDMI to FPD-Link III Bridge Serializer with HDCP

www.ti.com
DS90UH949-Q1
SNLS453 – NOVEMBER 2014
Register Maps (continued)
ADD
(dec)
162
ADD
(hex)
0xA2
Register Name
RX_BSTATUS1
163
0xA3 KSV_FIFO
192
0xC0 HDCP_DBG
Bit(s)
7:4
3
2:0
7:0
7
6
5
4
3
2
1
0
Table 10. Serial Control Bus Registers (continued)
Register
Type
R
R
R
RW
RW
RW
RW
RW
RW
Default
(hex)
0x00
0x00
0x00
0x00
Function
Description
Reserved.
MAX_CASC_E Maximum Cascade Exceeded: Indicates a topology error was detected. Indicates that
XCEEDED
more than seven levels of repeaters have been cascad-ed together.
Cascade
Depth
Cascade Depth: Indicates the number of attached levels of devices for the Repeater.
KSV_FIFO
KSV FIFO: Each read of the KSV FIFO returns one byte of the KSV FIFO list composed
by the downstream Receiver.
Reserved.
HDCP_I2C_T
O_DIS
HDCP I2C Timeout Disable: Setting this bit to a 1 will disable the bus timeout function in
the HDCP I2C master. When enabled, the bus timeout function allows the I2C master to
assume the bus is free if no signaling occurs for more than 1 second.
Reserved.
DIS_RI_SYNC Disable Ri Synchronization check: Ri is normally checked both before and after the start
of frame 128. The check at frame 127 ensures synchronization between the two. Setting
this bit to a 1 will disable the check at frame 127.
RGB_CHKSU Enable RBG video line checksum: Enables sending of ones-complement checksum for
M_EN
each 8-bit RBG data channel following end of each video data line.
FC_TESTMOD Frame Counter Testmode: Speeds up frame counter used for Pj and Ri verification.
E
When set to a 1, Pj is computed every 2 frames and Ri is computed every 16 frames.
When set to a 0, Pj is computed every 16 frames and Ri is computed every 128 frames.
TMR_SPEEDU Timer Speedup: Speed up HDCP authentication timers.
P
HDCP_I2C_FA HDCP I2C Fast Mode Enable Setting this bit to a 1 will enable the HDCP I2C Master in
ST
the HDCP Receiver to operation with Fast mode timing. If set to a 0, the I2C Master will
operation with Standard mode timing. This bit is mirrored in the IND_STS register.
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: DS90UH949-Q1
Submit Documentation Feedback
65