DS90UH949-Q1 Datasheet, PDF (38/87 Pages) Texas Instruments – 1080p HDMI to FPD-Link III Bridge Serializer with HDCP

DS90UH949-Q1
SNLS453 – NOVEMBER 2014
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Register Maps (continued)
ADD
(dec)
3
ADD
(hex)
0x03
Register Name
General
Configuration
4
0x04 Mode Select
Bit(s)
7
6
5
4
3
2
1
0
7
6
5
4:0
Table 10. Serial Control Bus Registers (continued)
Register
Type
RW
RW
RW
RW
RW
RW
RW
Default
(hex)
0xD2
0x80
Function
Description
Back channel
CRC Checker
Enable
I2C Remote
Write Auto
Acknowledge
Port0/Port1
Filter Enable
I2C Pass-
through
Port0/Port1
TMDS Clock
Auto
Failsafe State
CRC Error
Reset
Enable/disable back channel CRC Checker.
0: Disable.
1: Enable (default).
Reserved.
Automatically acknowledge I2C remote writes. When enabled, I2C writes to the
Deserializer (or any remote I2C Slave, if I2C PASS ALL is enabled) are immediately
acknowledged without waiting for the Deserializer to acknowledge the write. This allows
higher throughput on the I2C bus. Note: this mode will prevent any NACK from a remote
device from reaching the I2C master.
0: Disable (default).
1: Enable.
If PORT1_SEL is set, this register controls Port1 operation.
HS, VS, DE two-clock filter. When enabled, pulses less than two full TMDS clock cycles
on the DE, HS, and VS inputs will be rejected.
0: Filtering disable.
1: Filtering enable (default).
I2C pass-through mode. Read/Write transactions matching any entry in the Slave Alias
registers will be passed through to the remote Deserializer.
0: Pass-through disabled (default).
1: Pass-through enabled.
If PORT1_SEL is set, this register controls Port1 operation.
Reserved.
Switch over to internal oscillator in the absence of TMDS Clock.
0: Disable auto-switch.
1: Enable auto-switch (default).
Reserved.
Input failsafe state.
0: Failsafe to High.
1: Failsafe to Low (default).
Reserved.
Clear back channel CRC Error counters. This bit is NOT self-clearing.
0: Normal operation (default).
1: Clear counters.
Reserved.
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