5962-0924001VXC Datasheet, PDF (6/46 Pages) Texas Instruments – 12-Bit, 1-GSPS Analog-to-Digital Converter

ADS5400-SP
SLAS669C – SEPTEMBER 2010 – REVISED AUGUST 2012
www.ti.com
SWITCHING CHARACTERISTICS
Typical values at T_A = 25°C, Min and Max values over full temperature range T_C,MIN = –55°C to T_C,MAX = 125°C,
sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 1.5 V_PP differential clock
(unless otherwise noted)
PARAMETER
TEST CONDITIONS/NOTES
MIN
TYP
MAX UNIT
LVDS DIGITAL OUTPUTS (DATA, OVR/SYNCOUT, CLKOUT)
V_OD
Differential output voltage (±)
V_OC
Common mode output voltage
LVDS DIGITAL INPUTS (RESET)
Terminated 100 Ω differential
247
350
1.125
1.25
454 mV
1.375
V
V_ID
Differential input voltage (±)
V_IC
Common mode input voltage
R_IN
Input resistance
C_IN
Input capacitance
DIGITAL INPUTS (SCLK, SDIO, SDENB)
Each input pin
Each pin to ground
175
350
0.1
1.25
100
3.7
mV
2.4
V
Ω
pF
V_IH
High level input voltage
V_IL
Low level input voltage
I_IH
High level input current
I_IL
Low level input current
C_IN
Input capacitance
DIGITAL INPUTS ( ENEXTREF, ENPWD, ENA1BUS)
2
AVDD3 + 0.3
V
0
0.8
V
±1
μA
±1
μA
2.9
pF
V_IH
High level input voltage
V_IL
Low level input voltage
I_IH
High level input current
I_IL
Low level input current
C_IN
Input capacitance
DIGITAL OUTPUTS (SDIO, SDO)
~40kΩ internal pull-down
2
AVDD5 + 0.3
V
0
0.8
V
125
μA
20
μA
2.9
pF
V_OH
High level output voltage
V_OL
Low level output voltage
CLOCK INPUTS
I_OH = 250 µA
I_OL = 250 µA
2.8
V
0.4
V
R_IN
Differential input resistance
Input capacitance
C_IN
CLKINP, CLKINN
Estimated to ground from each
CLKIN pin, excluding soldered
packaged
100
130
4.8
190
Ω
pF
TIMING CHARACTERISTICS⁽¹⁾
Typical values at T_A = 25°C, Min and Max values over full temperature range T_C,MIN = –55°C to T_C,MAX = 125°C,
sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 1.5 V_PP differential clock
(unless otherwise noted)
PARAMETER
TEST CONDITIONS/NOTES
MIN
TYP
MAX UNIT
t_a
Aperture delay
Aperture jitter, rms
Uncertainty of sample point due to internal jitter
sources
250
ps
125
fs
Bus A, using Single Bus Mode
7
Latency
Bus A, using Dual Bus Mode Aligned
Bus B, using Dual Bus Mode Aligned
7.5
Cycles
8.5
Bus A and B, using Dual Bus Mode Staggered
7.5
(1) Timing parameters are specified by design or characterization, but not production tested.
6
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