5962-0924001VXC Datasheet, PDF (35/46 Pages) Texas Instruments – 12-Bit, 1-GSPS Analog-to-Digital Converter

ADS5400-SP
www.ti.com
80
f_IN = 100.33 MHz
75
70
f_IN = 901.13 MHz
SLAS669C – SEPTEMBER 2010 – REVISED AUGUST 2012
65
f_IN = 601.13 MHz
60
f_IN = 100.33 MHz
65
f_IN = 601.13 MHz
55
f_IN = 1498.5 MHz
60
f_IN = 1498.5 MHz
f_IN = 901.13 MHz
55
50
50
45
f_S = 1 GSPS
40
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Clock Common Mode − V
G016
Figure 35. ADS5400 SFDR vs Clock Common Mode
45
f_S = 1 GSPS
40
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Clock Common Mode − V
G017
Figure 36. ADS5400 SNR vs Clock Common Mode
To understand how to determine the required clock jitter, an example is useful. The ADS5400 is capable of
achieving 58.7 dBFS SNR at 850 MHz of analog input frequency. To achieve SNR at 850 MHz, the external
clock source rms jitter must be at least 210fs when combined with the 125fs of internal aperture jitter in order for
the total rms jitter to be 244fs. A summary of maximum recommended rms clock jitter as a function of analog
input frequency is provided in Table 18 (using 125fs of internal aperture jitter). The equations used to create the
table are also presented.
INPUT FREQUENCY
(MHz)
125
600
850
1200
1700
Table 18. Recommended RMS Clock Jitter
MEASURED SNR
(dBc)
58.1
57.8
57.7
56.6
54.7
TOTAL JITTER
(fs rms)
1585
318
244
196
172
MAXIMUM EXT CLOCK JITTER
(fs rms)
1580
342
210
151
119
Equation 1 and Equation 2 are used to estimate the required clock source jitter.
SNR (dBc) = -20 x LOG10 (2 x p x f_IN x j_TOTAL)
(1)
j_TOTAL = (j_ADC² + j_CLOCK²)^1/2
(2)
where:
j_TOTAL = the rms summation of the clock and ADC aperture jitter;
j_ADC = the ADC internal aperture jitter which is located in the data sheet;
j_CLOCK = the rms jitter of the clock at the clock input pins to the ADC; and
f_IN = the analog input frequency.
Notice that the SNR is a strong function of the analog input frequency, not the clock frequency. The slope of the
clock source edges can have a mild impact on SNR as well and is not taken into account for these estimates.
For this reason, maximizing clock source amplitudes at the ADC clock inputs is recommended, though not
required (faster slope is desirable for jitter-related SNR). For more information on clocking high-speed ADCs, see
Application Note SLWA034, Implementing a CDC7005 Low Jitter Clock Solution For High-Speed, High-IF ADC
Devices. Recommended clock distribution chips (CDCs) are the TI CDC7005 and CDCM7005. Depending on the
jitter requirements, a band pass filter (BPF) is sometimes required between the CDC and the ADC. If the
insertion loss of the BPF causes the clock amplitude to be too low for the ADC, or the clock source amplitude is
too low to begin with, an inexpensive amplifier can be placed between the CDC and the BPF.
Copyright © 2010–2012, Texas Instruments Incorporated
35
Product Folder Links: ADS5400-SP